W9864G6DB Datasheet, PDF (5/48 Pages) Winbond – 1M x 4 BANKS x 16 BITS SDRAM

W9864G6DB
5. PIN DESCRIPTION
BALL LOCATION PIN NAME FUNCTION
DESCRIPTION
M1, M2, N1, N2,
N6, N7, P1, P2, A0 − A11
P6, P7, R6,
Address
Multiplexed pins for row and column address. Row
address: A0 − A11. Column address: A0 − A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
M6, M7
BS0, BS1
Bank Select
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
A2, A6, B1, B7,
C1, C7, D1, D2,
D6, D7, E1, E7,
F1, F7, G1, G7
DQ0 −
DQ15
Data Input/
Output
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
L7
CS
Chip Select command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
K6
Row Address
RAS
Strobe
the clock RAS , CAS and WE define the
operation to be executed.
Column
K7
CAS
Address _{Referred to RAS}
Strobe
J7
J6, J5
K2
L1
A7, H6, R7
A1, H2, R1
B6, C2, E6, F2
B2, C6, E2, F6
G2, G6, H1, H7,
J1, K1, L2, L6
WE
UDQM
LDQM
CLK
CKE
VDD
VSS
VDDQ
VSSQ
Write Enable _{Referred to RAS}
Input/Output
Mask
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
Clock Inputs
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
Clock Enable When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
Ground
Ground for input buffers and logic circuit inside
DRAM.
Power (+3.3V) Separated power from VDD, to improve DQ noise
for I/O Buffer immunity.
Ground for I/O Separated ground from VSS, to improve DQ noise
Buffer
immunity.
NC No Connection No connection
Publication Release Date: January 27, 2003
-5-
Revision A1