W9864G6DB Datasheet, PDF (24/48 Pages) Winbond – 1M x 4 BANKS x 16 BITS SDRAM

W9864G6DB
11. OPERATING TIMING EXAMPLE
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
CLK
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CS
RAS
CAS
tRC
tRAS
tRC
tRP
tRAS
tRC
tRAS
tRP
tRC
tRP
tRAS
WE
BS0
BS1
tRCD
A10 RAa
RBb
tRCD
RAc
tRCD
RBd
tRCD
RAe
A0-A9 ^RAa
CAw
RBb
CBx
RAc
DQM
CAy
RBd
CBz
RAe
CKE
DQ
Bank #0 Active
Bank #1
Bank #2
Idle
Bank #3
tRRD
tAC
aw0 aw1 aw2 aw3
tRRD
tAC
bx0 bx1 bx2 bx3
tRRD
tAC
tAC
cy0 cy1 ^cy2 cy3
tRRD
Read
Precharge
Active
Read
Active
Read
Precharge
Active
Precharge
Read
Active
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