W9864G6DB Datasheet, PDF (25/48 Pages) Winbond – 1M x 4 BANKS x 16 BITS SDRAM

W9864G6DB
Operating Timing Example, continued
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge)
CLK
CS
RAS
CAS
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
tRC
tRAS
tRC
tRP
tRAS
tRC
tRAS
tRP
tRC
tRP
tRAS
WE
BS0
BS1
tRCD
A10 ^RAa
RBb
tRCD
tRCD
RAc
tRCD
RBd
RAe
A0-A9 RAa
DQM
CKE
DQ
CAw RBb
CBx
RAc
CAy
RBd
CBz
RAe
tAC
aw0 aw1 aw2 aw3
tAC
tAC
bx0 bx1 bx2 bx3
cy0 cy1 cy2 cy3
tAC
dz0
tRRD
tRRD
tRRD
tRRD
Bank #0
Bank #1
Bank #2
Bank #3
Active
Idle
Read
Active
AP*
Active
Read
* AP is the internal precharge start timing
Read
AP*
AP*
Active
Read
Active
- 25 -
Publication Release Date: January 27, 2003
Revision A1