W9864G6DB Datasheet, PDF (35/48 Pages) Winbond – 1M x 4 BANKS x 16 BITS SDRAM

W9864G6DB
Operating Timing Example, continued
Self Refresh Cycle
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
tRP
RAS
CAS
WE
BS0,1
A10
A0-A9
DQM
tSB
tCKS
tCKS
CKE
tCKS
DQ
Self Refresh Cycle
All Banks
Precharge
Self Refresh
Entry
tRC
No Operation Cycle
Arbitrary Cycle
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Publication Release Date: January 27, 2003
Revision A1