W9864G6DB Datasheet, PDF (41/48 Pages) Winbond – 1M x 4 BANKS x 16 BITS SDRAM

W9864G6DB
Operating Timing Example, continued
Timing Chart of Write to Read Cycle
In the case of Burst Length = 4
01 ^{2 3 4 5 6 7 8 9}
(1) CAS Latency = 2
( a ) Command
DQM
DQ
Write Read
D0
Q0 Q1 Q2 Q3
( b ) Command
DQM
DQ
Write
Read
D0 D1
Q0 Q1 Q2 Q3
10 11
(2) CAS Latency = 3
( a ) Command
DQM
DQ
( b ) Command
DQM
DQ
Write Read
D0
Write
Read
D0 D1
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
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Publication Release Date: January 27, 2003
Revision A1