W9864G6DB Datasheet, PDF (43/48 Pages) Winbond – 1M x 4 BANKS x 16 BITS SDRAM

W9864G6DB
Operating Timing Example, continued
Timing Chart of Burst Stop Cycle (Precharge Command)
In the case of Burst Lenght = 8
0 1 2 3 4 5 6 7 8 9 10 11
(1) Read cycle
( a )CAS latency =2
Commad
Read
PRCG
DQ
( b )CAS latency = 3
Commad
Read
Q0 Q1 Q2 Q3 Q4
PRCG
DQ
(2) Write cycle
Q0 Q1 Q2 Q3 Q4
( a ) CAS latency =2
Commad
DQM
Write
PRCG
tWR
DQ _{D0 D1 D2 D3 D4}
( b ) CAS latency = 3
Commad
Write
PRCG
tWR
DQM
DQ _{D0 D1 D2 D3} D4
Note: PRCG represents the Precharge command
- 43 -
Publication Release Date: January 27, 2003
Revision A1