W83627EHF_0611 Datasheet, PDF (27/144 Pages) Winbond – WINBOND LPC I/O

W83627EHF/EF, W83627EHG/EG
5.10.4 GPIO-3 Interface
SYMBOL
GP30
GP31
GP32
RSTOUT2#
SCL
GP33
RSTOUT3#
SDA
GP34
RSTOUT4#
GP35
GP36
GP37
PIN
I/O
92 I/OD_12t
91 I/OD_12t
I/OD_12t
90 OUT₁₂
IN_ts
I/OD_12t
89 OUT₁₂
I/OD_12ts
88
I/OD_12t
OUT₁₂
87 I/OD_12t
69 I/OD_12t
64 I/OD_12t
FUNCTION
General purpose I/O port 3 bit 0.
General purpose I/O port 3 bit 1
General purpose I/O port 3 bit 2.
Secondary LRESET# output 2.
Serial Bus clock.
General purpose I/O port 3 bit 3.
Secondary LRESET# output 3.
Serial bus bi-directional Data.
General purpose I/O port 3 bit 4.
Secondary LRESET# output 4.
General purpose I/O port 3 bit 5
General purpose I/O port 3 bit 6
General purpose I/O port 3 bit 7
5.10.5 GPIO-4 Interface
see 5.4 Serial Port B
5.10.6 GPIO-5 Interface
SYMBOL PIN
I/O
GP50
I/O_12t
EN_VRM10 77
IN_cd
WDTO#
OUT₁₂
GP51
75
I/OD_12t
RSMRST#
OD₁₂
GP52
SUSB#
73
I/OD_12t
IN_t
GP53
PSON#
72
I/OD_12t
OD₁₂
GP54
PWROK
71
I/OD_12t
OD₁₂
FUNCTION
General purpose I/O port 5 bit 0.
During VSB power reset (RSMRST), this pin is pulled down
internally and is defined as VID transition voltage level, which
provides the value for CR2C bit 3. A 1 kΩ is reserved to pull
down and a 1 kΩ is recommended if intends to pull up.
Watchdog timer output signal.
General purpose I/O port 5 bit 1.
Resume reset signal output.
General purpose I/O port 5 bit 2.
System S3 states input.
General purpose I/O port 5 bit 3.
This pin generates the PWRCTL# signal while the power failure.
General purpose I/O port 5 bit 4.
This pin generates the PWROK signal while the VCC come in.
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Publication Release Date: Nov. 2006
Revision 1.3