W83627EHF_0611 Datasheet, PDF (15/144 Pages) Winbond – WINBOND LPC I/O

W83627EHF/EF, W83627EHG/EG
5. PIN DESCRIPTION
Note: Please refer to Section 8.2 DC CHARACTERISTICS for details.
AOUT
AIN
IN_cs
IN_t
IN_td
IN_ts
IN_tsp3
IN_tu
I/O_8t
I/O_12t
I/OD_12ts
I/OD_16cs
I/OD_24t
OUT₈
OUT₁₂
OUT₂₄
OD₈
OD₁₂
OD₂₄
- Analog output pin
- Analog input pin
- CMOS level Schmitt-triggered input pin
- TTL level input pin
- TTL level input pin with internal pull down resistor
- TTL level Schmitt-triggered input pin
- 3.3V TTL level Schmitt-triggered input pin
- TTL level input pin with internal pull up resistor
- TTL level bi-directional pin with 8 mA source-sink capability
-3.3V TTL level bi-directional pin with 12 mA source-sink capability
- 3.3V TTL level bi-directional Schmitt-triggered pin. Open-drain output with 12 mA sink capability
- CMOS level Schmitt-triggered bi-directional pin. Open-drain output with 16 mA sink capability
- TTL level bi-directional pin. Open-drain output with 24 mA sink capability
- TTL level output pin with 8 mA source-sink capability
-3.3V TTL level output pin with 12 mA source-sink capability
- TTL level output pin with 24 mA source-sink capability
- Open-drain output pin with 8 mA sink capability
- Open-drain output pin with 12 mA sink capability
- Open-drain output pin with 24 mA sink capability
5.1 LPC Interface
SYMBOL PIN
I/O
IOCLK
18
IN_t
PME#
PCICLK
LDRQ#
SERIRQ
LAD[3:0]
86
OD₁₂
21
IN_ts
22
O₁₂
23
I/OD_12t
24-
27
I/O_12t
LFRAME# 29
IN_ts
LRESET# 30
IN_ts
FUNCTION
System clock input, which is selective by the register according
to the input frequency either 24MHz or 48MHz. Default is
48MHz.
Generated PME event.
PCI clock 33 MHz input.
Encoded DMA Request signal.
Serial IRQ Input/Output.
These signal lines communicate address, control, and data
information over the LPC bus between a host and a peripheral.
Indicates start of a new cycle or termination of a broken cycle.
Reset signal. It can connect to PCIRST# signal on the host.
Publication Release Date: Nov. 2006
-9-
Revision 1.3