UM6522A Datasheet, PDF (9/17 Pages) UMC Corporation – Versatile Interface Adapter (VIA)

GD ^UMC
UM6522/A
Handshake Control of Data Transfer
The UM6522/A allows positive control of data transfer
between the System processor and peripheral devices
through the Operation of “handshake” lines. Port A lines
(CAI, CA2) handshake data on both a read and a write
Operation while the Port B lines (CBI, CB2) handshake
on a write Operation only.
Read Handshake
Positive control of data transfer from peripheral devices
into the System processor tan be accomplished very effec-
tively using Read Handshaking. In this case, the peripheral
device must generate the equivalent of a “Data Ready”
Signal to the processor signifying that valid data is present
on the peripheral Port. This Signal normally interrupts
REG 0-ORB/IRB
the processor, which then reads the data, causing generation
of a “Data Taken” Signal. The peripheral device responds
by making new data available. This process continues
until the data transfer is complete.
In the UM6522/A, automatic “ R e a d ” H a n d s h a k i n g i s
possible on the Peripheral A port only. The CA1 interrupt
input pin accepts the “Data Ready” Signal and CA2
generates the “Data Taken” Signal. The “Data Ready”
Signal will set an internal flag which may interrupt the
processor or which may be polled under program control.
‘The “Data Taken” Signal tan either be a pulse or a level
which is set low by the System processor and is cleared
by the “Data Ready” Signal. These Options are shown
in Figure 12 which illustrates the normal Read Handshaking
sequence.
REG 1 -ORA/IRA
OUTPUT REGISTER “A” IORA)
OR
INPUT REGISTER
OfJRB=“l” (OUTPUT) ^{MPU writer Output}
ORB but no effect
On Pin Level untll
Figure 9. Output Register B (ORB) Input Register B (IRBI
REG 2 (DDRB) AND REG 3 (DDRA)
1^PBOIPAO
PBl/PAl
PB2iPA2
ODRA=~‘~” IOuTPuTt
(Input lalching disabled)
oo~~z*‘, 8’ f0uTpuT)
(Input latching enabled)
ODRA=‘*~’ ~INPUTI
(Input latchlw disabledl
DORA=“O” (INPUT)
llnput latching enabledl
MPU writes Output
Level IORA)
MPU writes into
ORA. but no effect
on pin level. until
DORA changed
MPU reads level on PA pl”.
MPU rea& IRA bit which is
the ievel of the PA pin at
the time of the last CA1
active transition.
MPU reads level on PA Pin.
MPU reads IRA bit which is
the level of the PA pin at
the time of the last CA1
actiue transition
Figure 10. Output Register A (C)RA),
Input Register A (IRAI
“0” ASSOCIATED PB/PA PIN IS AN INPUT
(HIGH-IMPEDANCE)
“1” ASSOCIATED PB/PA PIN IS AN OUTPUT
WHOSE LEVEL IS DETERMINED BY
Figure 11. Data Direction Registers (DDRB, DDRA)
Write Handshake
The sequence of operations which allows handshaking data
from the System processor to a peripheral device is very
similar to that described for Read Handshaking. However,
for Write Handshaking, the UM6522/A generates the “Data
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