UM6522A Datasheet, PDF (14/17 Pages) UMC Corporation – Versatile Interface Adapter (VIA)

UMC
UMSSZZ/A
Associated with each interrupt flag is an interrupt enable
bit. This tan be set or cleared by the processor to enable
interrupting the processor from the corresponding interrupt
flag. If an interrupt flag is set to a logic “1” byan interrupt-
ing condition, and the corresponding interrupt enable bit
is set to a “l”, the Interrupt Request Output (m) will go
low. IRQ is an “open-collector” o u t p u t which tan b e
wire-ORed to other devices in the System to interrupt the
processor.
In the UM6522/A, all the interrupt flags are contained in
one register. In addition, bit 7 of this register will be read
as a logic “1” when an interrupt exists within the Chip. This
allows very convenient polling of several devices within
a System to locate the Source of an interrupt.
WRITE TZC-H
OPERATION
PE6 INPUT
~
IRQ OUTPUT
NI
N-l
I
N-2
l{ _{I O}
Figure 21. Timer 2 Pulse Counting Mode
Reg IO - H Reg 10 - Shift Register
Reg 11 - Auxiliary Cuntrol Register
SHIFT REGISTER BITS
SHIFT REGISTER MODE CONTROL
NOTES:
1. WHEN SHIFTING OUT. BIT 7 IS THE FIRST BIT
OUT AND SIMULTANEOUSLY IS ROTATED BACK
BIT 0 AND SHIFTED TOWARDS BIT 7.
2. WHEN SHIFTING IN. BITS INITIALLY ENTER
BIT 0 AND ARE SHIFTED TOWARDS BIT 7.
SHIFT OUT UNOER C
Figure 22. SR and ACR Control Bits
.
SR Disabled (000)
The 000 mode is used to disable the Shift Register. In this
T2 latch (N).
mode the microprocessor tan wrlte or read the SR, but the
shifting operating is disabled and Operation of CB1 and CB2
The shifting Operation is triggered by writing or reading
is controlled by the appropriate bits in the Peripheral
the shift register. Data is shifted first into the low Order
Control Register (PCR). In this mode the SR Interrupt
bit of SR and is then shifted into the next higher Order
Flag is disabled (held to a logic “0”).
bit of the shift register on the negative-going edge of each
clock pulse. The input data should Change before the
Shift in Under Cuntrol of T2 (001)
positive-going edge of the CB1 clock pulse. This data is
In the 001 mode the shifting rate is controlled by the low
Order 8 bits of “T2”. Shift Pulses are generated on the
CB1 Pin to control shifting in external devices. The time
between transitions of this output clock is a function of
shifted into the shift register during the 42 clock cycle
following the positive-going edge of the CB1 clock pulse.
After 8 CB1 clock pulses, the shift register interrupt flag
will be set and IRQ will go low.
the System clock period and the contents of the low Order
WRITE OR READ
SHIFT REG.
CB1 OUTPUT
SHIFT CLOCK
CB2 INPUT
DATA