UM6522A Datasheet, PDF (11/17 Pages) UMC Corporation – Versatile Interface Adapter (VIA)

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pin each time it “firnes-out.” Esch of these modes is
discussed separately below.
The Tl counter is depicted in Figure 15 and the latches in
Figure 16
Reg 4 - Timer 1 Low-Order Counter
UM6522/A
Two bits are provided in the Auxiliary Control Register
(bits 6 and 7) to allow selection of the Tl operating modes.
The four possible modes are depicted in Figure 17.
Reg 5 - Timer 1 High-Order Counter
COUNT VALUE
WRITE
-8 BITS ARE LOA&l I N T O T l L O W - O R D E R L A T C H E S .
CATCH C O N T E N T S A R E T R A N S F E R R E D I N T O L O W
O R D E R C O U N T E R A T T H E TIME T H E H I G H O R D E R
C O U N T E R IS LOADED (REG. 51.
READ - 8 B I T S F R O M T l L O W - O R D E R C O U N T E R ARE T R A N S -
FERRED TO MPU. IN ADDITION. Tl INTERRUPT FLAG
IS RESET (BIT 6 IN INTERRUPT FLAG REGISTER).
WRITE -6 BITS LOADED INTO ;, HIGt%ORDER LATCHES. ALSO,
AT THIS TIME BOTH HIGH AND LOW-ORDER LATCHES
ARE TRANSFERRED INTO THE Tl COUNTER. AND
INITIATES COUNTDOWN Tl INTERRUPT FLAG IS A L S O
RESET
READ - 8 BITS FROM Tl HIGH-ORDER COUNTER TRANSFERRED
TO MPU.
Figure 15. Tl Counter Registers
Reg 6 - Timer 1 Low-Order Latches
1¹
2
4
8
16
COUNT VALUE
l-
Reg 7 - Timer 1 High-Order Latches
COUNT VALLJE
WRITE-6 B I T S A R E L O A D E D I N T O T l L O W - O R D E R L A T C H E S
T H I S O P E R A T I O N IS N O D I F F E R E N T FOLLOWING A
WRITE INTO REG 4
WRITE-6 BITS LOADED INTO Tl HIGH-ORDER LATCHES. UNLIKE
REG. 4 OPERATION. NO LATCH-TO-COUNTER TRANS
FERS TAKE PLACE.
R E A D - 6 BITS FAOM Tl LOW-OADER L A T C H E S T R A N S F E R R E D
T O MPU. UNLIKE AEG 4 OPERATION, THIS D O E S N C T
CAUSE RESET OF Tl INTERRUPT F LAG.
READ- 6 BITS FROM Tl HIGH-ORDER LATCHES ARE TRANS-
FERRED TO MPU
Figure 16. Tl Latch Registers
Reg 11 - Auxiliary Control Register
Figure 17. Auxiliary Control Register
Note. The processor does not wfite directly to the Iow order counter (TlC-L). Instead. this half of the counter is loaded automatically from
the low Order latch when the processor writes to the high Order counter In fact, it may not be necessary to write to the low Order counter in
some applications since the timing Operation is triggered by writing to the high Order counter.
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