UM6522A Datasheet, PDF (7/17 Pages) UMC Corporation – Versatile Interface Adapter (VIA)

GD ^UMC
Pin Description
RES (Reset)
The reset input clears all internal registers to logic “0”
(except Tl and T2 latches and counters and the Shift
Register). This places all peripheral interface lines in the
input state, disables the timers, shift register, etc. and
disables interrupting from the Chip.
$2 (Input Glock)
The input clock is the System $2 clock and is used to
trigger all data transfers between the System processor and
the UM6522lA.
Rm (Read/Write)
The direction of the data transfers between the UM6522/A
and the System processor is controlled by the Rm Iine. If
R/W is low, data will be transferred out of the processor
into the selected UM6522/A register (write Operation). If
Rm is high and the chip is selected, data will be transferred
out of the UM6522/A (read Operation).
DBO-DB7 (Data Bus)
The eight bi-directional data bus lines are used to transfer
data between the UM6522/A and the System processor.
During read cycles, the contents of the selected UM6522/A
UMSSZZ/A
register are placed on the data bus lines and transferred
into the processor. During write cycles, these lines
are high-impedance inputs and data IS transferred from
the processor into the selected register. When the
UM6522/A is unselected, the data bus lines are high-
impedance.
CSl, CS2 (Chip Selects)
The two chip select inputs are normally connected to
processor address lines either directly or through decoding.
The selected UM6522/A register will be accessed when
CS1 is high and CS2 is low.
RSO- RS3 (Register Selects)
The four Register Select inputs permit the System processor
to select one of the 16 internal registers of the UM6522/A,
as shown in Figure 6.
IRQ (Interrupt Request)
The Interrupt Request output goes low whenever an
internal interrupt flag is set and the corresponding interrupt
enable bit is a logic “1”. This output is “opendrain” to
allow the interrupt request Signal to be wire-ORed with
other equivalent Signals in the System.
Register
Number
0
1
RS Coding
RS3
RS2
RSI
RSO
0
0
I
0
0
0
0
I
I
I
0
1
Register
Desig.
ORB/IRB
ORAIIRA
Description
Write
Read
Output Register “B”
I
Output Register “A”
Input Reaister “ B ”
I
Input Register “A”
15 1 1
1
1 1 ORAIIRA
Same as Reg 1 Except No. “Handshake”
I
Figure 6. UM6522/A Internal Register Summary
.
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