UM6522A Datasheet, PDF (17/17 Pages) UMC Corporation – Versatile Interface Adapter (VIA)

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The Interrupt Flag Register (IFR) and Interrupt Enable
Register (IERI are depicted in Figures 25 and 26, respec-
tively.
The IFR may be read directly by the processor. In addi-
tion, individual flag bits may be cleared by writing a “1”
into the appropriate bit of the IFR. When the proper
chip select and register Signals are applied to the Chip, the
contents of this register are placrxf on the data bus. Bit 7
indicates the Status of the IRQ output. This bit cor-
responds to the logic function. IRQ = IFR6 x IER6 +
IFR5 x IER5 + IFR4 x IER4 + IFR3 x IER3 + IFR2 x
IER2 + IFRl x IERl + IFRO x IERO. Note: X = l o g i c
AND, += Logic OR.
T h e IFR bit 7 is not a flag. Therefore, this bit is not
directly cleared by writing a logic “1” into it, lt tan only
be cleared by Clearing all the flags in the register or by
disabling all the active interrupts as discussed in the next
section.
For each interrupt flag in IFR, there is a corresponding
bit in the Interrupt Enable Register. The System processor
UM6522/A
tan Set or clear selected bits in this register to facilitate
controlling individual interrupts without affecting others.
This is accomplished by writing to address 1110 (IER
address). If bit 7 of the data placed on the System data
bus during this write Operation is a “O”, each “1 ” in bits 6
through 0 clears the corresponding bit in the Interrupt
Enable Register. For each “zero” in bits 6 through 0, the
corresponding bit is unaffected.
Setting selected bits in the Interrupt Enable Register is
accomplished by writing to the same address with bit 7 in
the data word set to a logic “1”. In this case, each “1” in
bits 6 through 0 will set the corresponding bit. For each
“Zero”, the corresponding bit will be unaffected. The
individual control of the setting and Clearing operations
allows very convenient control of the interrupts during
System Operation.
In addition to setting and Clearing IER bits, the processor
tan read the contents of this register by placing the proper
address on the register select and chip select inputs with the
Rmline high. Bit 7 will be read as a logic “1 ”
Reg 13 - Interrupt Flag Register
Reg 14 - Interrupt Enable Register
SET BY
CLEAAEO BY
CA1
. IF THE CA2KB2 CONTROL IN THE PCR IS S E L E C T E D A S
“INDEPENDENT” INTERRUPT INPUT, THEN READING OR
W R I T I N G T H E O U T P U T R E G I S T E R ORA/ORB W I L L N O T
C L E A A T H E F L A G B I T . INSTEAD. T H E B I T M U S T B E
C L E A A E D B Y W R I T I N G I N T O T H E IFR. AS DESCRIBED
PREVIOUSLY,
Figure 25. Interrupt Flag Register (IFRI
Notes:
1 . I F B I T 7 ISA”O”,THEN EACH”1”INBlT.S0.6DISABLESTHE
CORRESPONDING INTERRUPT.
2. IF BIT 7 IS A “l”,THEN EACH “1” IN BITSO-6 E N A B L E S T H E
COARESPONDING INTERRUPT.
3. IF A READ OF THIS REGISTER IS DONE, BIT 7 WILL BE “1”
A N D A L L O T H E R B I T S W I L L R E F L E C T THEIR ENABLEI
DISABLE STATE.
Figure 26. Interrupt Enable Register (IER)
Ordering Information
Part Number
UM6522
UM6522A
Frequency
1 MHz
2 MHz
5-34
Package
40L DIP
40L DIP