UM6522A Datasheet, PDF (16/17 Pages) UMC Corporation – Versatile Interface Adapter (VIA)

GD ^UMC
UMSSZZ/A
Shift Out Under Control of T2 (1011
In mode 101 the shift rate is controlled by TZ (as in the
previous model. However, with each read or write of
the shift register the SR Counter is reset and 8 bits are
shifted onto CB2. At the same time, 8 shift pulses are
.-
generated on CB1 to control shifting in external devices.
After the 8 shift pulses, shifting is disabled, the SR
Interrupt Flag is set and CB2 remains at the last data
level.
$2
CLOCK
WRITE SR
OPERATION
CB1 OUTPUT
SHIFT CLOCK
CB2 INPUT
DATA
IRQ
Figure 24-2 Shift Register Output Modes
Shift Out Under Control of 9 2 (1 IO)
In mode 110, the shift rate is controlled by the $2 System clock.
WRITE SR
OPERATION
CB1 OUTPUT
SHIFT CLOCK
CB2 INPUT
DATA
IRQ
Figure 24-3 Shift Register Output Modes
Shift Out Under Control of External CB1 Glock (111)
In mode 111, shifting is controlled by pulses applied to
the CB1 pin by an external device. The SR counter sets
the SR Interrupt flag each time it counts 8 pulses but
it does not disable the shrfting function. Esch time the
microorocesor writes or reads the shift register, the SR
Interrupt flag is reset and the SR counter is initialized
to begin counting the next 8 shift pulses on pin GBl.
After 8 shift pulses, the interrupt flag is set. The micro-
processor tan then load the shift register with the next
byte of data.
dJ2
WRITE SR
OPERATION _
SHIFT CLOCK
CB2 OUTPUT
-
IRQ
Figure 24-4 Shift Register Output Modes