UM6522A Datasheet, PDF (15/17 Pages) UMC Corporation – Versatile Interface Adapter (VIA)

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Shift in Under Control of $2 (010)
In mode 010 the shift rate is a direct function of the System
clock frequency. CB1 becomes an output which generates
shift pulses for controlling external devices. Timer 2 op-
erates as an independent interval timer and has no effect
on SR. The shifting Operation is trlggered by reading or
UMSSZZ/A
writing the Shift Register. Data is shifted first into bit
0 and is then shifted into the next higher Order bit of the
shift register on the trailing edge of each 42 clock pulse.
After 8 clock pulses, the shift register interrupt flag will
be set, and the output clock pulses on CB1 will stop.
REAO SR
OPERATION
CB1 OUTPUT
SHIFT CLOCK
CB2 INPUT
DATA
Figure 23-2 Shift Register Input Modes
Shift in Under C o n t r o l o f E x t e r n a t CB1 Glock (Oll)
In mode Oll CB1 becomes an input. This allows an ex-
ternal device to load the shift register at its own Pace.
The shift register counter will interrupt the processor
each time 8 bits have been shifted in. However, the shift
register counter does not stop the shifting Operation;
it acts simply as a pulse counter. Reading or writing the
Shift Register resets the Interrupt flag and initializes the
SR counter to count another 8 pulses.
Note that the data is shifted durrng the first System clock
cycle following the positive-going edge of the CB1 shift
pulse. For this reason, data must be held stable during
the first full cycle after CB1 goes high.
CB1 OUTPUT
SHIFT CLOCK
Figure 23-3 Shift Register Input Modes
Shift Out Free-Running at T2 Rate (1001
Mode 100 is very similar to mode 101 in which the shift
rate is set by T2. However, in mode 100 the SR Counter
does not stop the shift Operation. Since Shift Register
bit 7 (SR7) is circulated back into bit 0, the 8 bits loaded
into the shift register will be clocked onto CR2 repeatedly.
In this mode the shift register counter is disabled, and
IRQ is never Set.
WRITE SR
OPERATION
CB1 OUTPUT
SHIFT CLOCK
CB2 INPUT
DATA
Figure 24-1 Shift Register Output Modes
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