UM6522A Datasheet, PDF (8/17 Pages) UMC Corporation – Versatile Interface Adapter (VIA)

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PAO-PA7 [Peripheral A Port)
The Peripheral A port consists of 8 lines which tan be
individually programmed to act as inputs or Outputs under
control of a Data Direction Register. The polarity of
output pins is controlled by an Output Register and input
data may be latched into an internal register under control
of the CA1 Iine. All of these modes of Operation arecon-
trolled by the System processor through the internal control
registers. These lines represent one Standard TTL load in
the input mode and will drive one Standard TTL load in the
output mode. Figure 7 illustrates the output circuit.
CAl, CA2 (Periphere1 A Cmtrol Lines)
The two Peripheral A control lines act as interrupt inputs
or as handshake Outputs. Esch line controls an internal
interrupt flag with a corresponding interrupt enable bit. In
addition, CA1 controls the latching of data on Peripheral
A port input lines. CA1 is a high impedance input only;
while CA2 represents one Standard TTL load in the input
mode. CA2 will drive one Standard TTL load in the output
mode.
PBO-PB7 (Peripheral B Port)
The Peripheral B port consists of eight bi-directional lines
which are controlled by an output register and a data direc-
tion register in much the same manner as the PA Port. In
addition, the PB7 output Signal tan be controlled by one
of the interval timers while the second t,imer tan be pro-
grammed to count pulses on the PB6 pin. Peripheral B
lines represent one Standard TTL load in the input mode
and will drive one Standard TTL load in the output mode.
In addition, they are capable of sourcing 1 .OmA at 1.5VDC
in the output mode to allow the Outputs to directly drive
Darlington transistor circuits Figure 8 is the circuit
schemat rc.
CBl, CB2 (Peripheral B Control Lines)
The Peripheral B control lines act as interrupt inputs or
as handshake Outputs. As with CA1 andCA2, each line
controls an interrupt flag with a corresponding interrupt
enable bit. In addition, these lines act asa serial port under
control of the Shift Register These lines represent one
Standard TTL load in the input mode and will drive one
Standard TTL load in the output mode. Unlike PBO-PB7.
CB1 and CB2 cannot drive Darlington transistor circuits.
I/O CONTROL
OUTPUT DATA
PAO-PA7 CA2
INPUT/
OUTPUT
CONTROL
PBO-PB7
GBl. CB2
INPUT DATA
Figure 7. Peripheral A Port Output Circuit
Figure 8. Peripheral B Port Output Circuit
Functional Description
Port A and Port B Operation
Esch B-bit peripheral port has a Data Direction Register
(DDRA, DDRB) for specifying whether the peripheral pins
are to act as inputs or Outputs. A “0” in a bit of the Data
Direction Register Causes the corresponding peripheral
pin to act as an input. A “1” Causes the pin to act as an
output.
When programmed as an output each peripheral pin is also
controlled by a corresponding bit in the Output Register
(ORA’ ORB). A “1” in the Output Register Causes the out-
put to go high, and a “0” Causes the output to go low. Data
may be written into Output Register bits corresponding
to pins which are programmed as inputs. In this case,
however, the output Signal is unaffected.
Reading a peripheral port Causes the contents of the Input
Register (IRA, IRB) to be transferred onto the Data Bus.
With input latching disabled, IRA will always reflect the
levels on the PA Pins. With input latching enabled and the
selected active transition on CA1 having occurred, IRA
will contain the data present on the PA lines at the time
of the transition. Once IRA is read, however, it will appear
transparent, reflecting the current state of the PA lines
until the next “latching” transition.
The IRB register operates similar to the IRA register.
However, for pins programmed as Outputs there is a dif-
ference. When reading IRA, the level on the pin determines
whether a “0” or a “1” is sensed. When reading IRB,
however, the bit stored in the output register, ORB, is the
bit sensed. Thus, for Outputs which have large loading
effects and which pull an output “1” down or which pull
an output “0” up, reading IRA may result in reading a “0”
when a “1” was actually programmed, and reading a “1”
when a “0” was programmed. Reading I RB, on the other
hand, will read the “1” or “0” level actually programmed,
no matter what the loading on the pin.
Figures 9, 10 and 11 illustrate the formats of the port
registers. In addition, the input latching modes are selected
by the Auxiliary Control Register (Figure 17.)