UM6522A Datasheet, PDF (13/17 Pages) UMC Corporation – Versatile Interface Adapter (VIA)

4!D ^UMC
Timer 2 Operation
Timer 2 operates as an interval timer (in the “oneshot”
mode only), or as a counter for counting negative pulses
on the PB6 peripheral pin. A Single control bit is provided
in the Auxiliary Control Regkter to select between these
two modes. This timer is comprised of a “write-only”
low-Order latch (T2L- L), a “read-only” low-Order counter
and a read/write high Order counter. The counter registers
act as a 16-bit counter which decrements at the $2 rate.
Figure 20 illustrates the T2 Counter Registers.
Timer 2 One-Shot Mode
As an interval timer, T2 operates in the “one-shot” mode
Reg 8 - Timer 2 Low-Order Counter
UM6522/A
similar to Timer 1. In this mode, T2 provides a Single
interrupt for each “write T2C- H” operatron. After timing
out, (reading 0) the counters “roll-over” to all 1’s (FFFF,,)
and continue decrementing, allowing the user to read
them and determine how lang T2 interrupt has been set.
However, setting of the interrupt flag will be disabled
after initial time-out so that it will not be set by the
counter continuing to decrement through Zero. The
processor must rewrite T2C-H to enable setting of the
interrupt flag. The interrupt flag is cleared by reading
T2C-L or by writing T2CH. Timing for this Operation
is shown in Figure 18.
Reg 9 - Timer 2 High-Order Counter
1
2
4
8
16
COLJNT VALUE
32
64
128 ₁
WRITE - 8 BITS LOADED INTO T2 LOW-ORDER LATCHES.
READ -8 BITS FROM T2 LOW-ORDER COUNTER TRANS-
FERRED TO MPU. T2 INTERRUPT FLAG IS RESET.
- C O U N T VALUE
WRITE - 8 BITS LOADED INTO T2 HIGH-ORDER COUNTER.
ALSO, LOW-ORDER LATCHES TRANSFERRED TO
LOW-ORDER COUNTER. IN ADDITION, T2 INTER-
RUPT FLAG IS RESET.
READ - 8 BITS FROM T2 HIGH-ORDER COUNTER TRANS-
FERAED TO MPU.
Figure 20. T2 bunter Registers
Timer 2 Pulse Counting Mode
In the pulse counting mode, T2 serves primarily to count
a predetermined number of negative-going pulses on PB6.
This is accomplished by first loading a number into T2.
Writing into T2CH clears the interrupt flag and allows the
counter to decrement each time a pulse is applied to PB6.
The interrupt flag will be set when T2 reaches Zero. At this
time, the counter will continue to decrement with each
pulse on PB6. However, it is necessary to rewrite T2C-H
to allow the interrupt flag to be set on subsequent down-
counting operations. Timing for this mode is shown in
Figure 21. The pulse must be low on the leading edge of
42.
Shift Register Operation
The Shift Register (SR) performs serial data transfer
into and out of the CB2 pin under control of an internal
modulo-8 counter. Shift pulses tan be applied to the
CB1 pin from an external Source or, with the proper mode
selection, shift pulses generated internally will appear on
the CB1 pin for controlling external devices.
The control bits which select the various shift register
operating modes are located in the Auxiliary Control
Register. Figure 22 illustrates the configuration of the
SR data bitsand the SR control bits of the ACR.
Figures and 24 illustrate the Operation of the various
shift register modes.
Interrupt Opetatlon
Controlling interrupts within the UM6522/A involves three
principal operations. These are flagging the interrupts,
enabling interrupts and signaling to the processor that
an active interrupt exists within the Chip. Interrupt flags
are set by interrupting conditions which exist within the
chip or on inputs to the Chip. These flags normally remain
set until the interrupt has been serviced. To determine the
source of an interrupt, the microprocessor must examine
these flags in Order from highest to lowest priority. This is
accomplished by reading the flag register into the processor
accumulator, shifting this register either right or left and
then using conditional branch instructions to detect an
active interrupt.
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