UM6522A Datasheet, PDF (10/17 Pages) UMC Corporation – Versatile Interface Adapter (VIA)

Ready” Signal and the peripheral device must respond
with the “Data Taken” Signal. This tan be accomplished
on both the PA port and the PB port on the UM6522/A.
CA2 or CB2 act as a “Data Ready” output in either the
handshake mode or pulse mode and CA1 or CB1 accept
the “Data Taken” Signal from the peripheral device, setting
UM6522/A
the interrupt flag and Clearing the “Data Ready” output.
This sequence is shown in Figure 13.
Selection of operatrng modes for CAI, CA2, CB1 , and CB2
is accomplished by the Peripheral Control Register (Figure
14).
D A T A R E A D Y [CAl)
IRQ OUTPUT
READ IRA
OPERATION
“DATA TAKEN”
I
HANDSHAKE MODE
l
ICA2)
“DATA TAKEN”
PULSE MODE
(CA21
Figure 12. Read Handshake Timing (Port A, Only)
WRITE ORA. ORB
OPERATION
“DATA READY” -
1
HANDSHAKE MODE
lCA2. CB21
“DATA READY”
PULSE MODE
I
ICA2, CB21
“DATA TAKEN”
(CAl. CBl)
IRQ OUTPUT
Figure 13. Write Handshake Timing
REG 12 - PERIPHERAL CONTROL REGISTER
I
1
1
CB2 CONTROL
7 16 15 1 OPERATION
0 IO IO ( INmyc~NE>AT!VE. ACTIVE EDGE
-~
0 I 0 I i I INOEPENDENT INTERRUPT
INPUT NcG EDGE
0 1 0 INPUT POSITIVE ACTIVE EDGE
0 1 1 INDEPENDENT INTERRUPT
INPUT POS EDGE
1 0 0 HANDSHAKE OUTPUT
1 0 1 PULSE OUTPUT
1 1 0 LOW OUTPUT
1 1 1 HIGH OUTPUT
CB1 I N T E R R U P T C O N T R O L -
0 = NEGATIVE ACTIVE EDGE
1 = POSITIVE ACTIVE EDGE
(SEE NOTE ACCOMPANYING FIGURE 251
CA1 INTERRUPT CONTROL
0 = NEGATIVE ACTIVE EDGE
1 = POSITIVE ACTIVE EDGE
CA2 CONTROL
Figure 14. CAI, CA2, CBI, CB2 Control
Timer Operation
Interval Timer, Tl, consists of two X-Bit latches and a 16-bit
decrement at the $2 clock rate. Upon reaching “zero”, an
interrupt flag will be set, and IRQ will go low if the inter-
rupt decrements at the 42 clock rate. Upon reaching
“Zero” an interrupt flag will be set, and IRQ will go low
if the interrupt is enabled. The timer will then disable any
further interrupts, or (when programmed to) will autom-
atically transfer the contents of the latches into the counter
and begin to decrement again. In addition, the timer may
be programmed to invert the output Signal on a peripheral
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