UM6522A Datasheet, PDF (12/17 Pages) UMC Corporation – Versatile Interface Adapter (VIA)

UM6522/A
42 JlJ-1
WRITE TIC-H
I
OPERATION
” 00;;;;;
(Tl, ONLY)
Tl COUNT
TZ COUNT
Figure 18. Timer 1 and Timer 2 One-Shot Mode Timing
Timer 1 One-Shot Mode
The interval timer one-shot mode allows generation of a
Single interrupt for each Timer load Operation. In addition,
Timer 1 tan be programmed to produce a Single negative
pulse on PB7.
To generate a Single interrupt ACR bits 6 and 7 must be
“O”, then either TI L-L or TIC-L must be written with the
low-Order count value. (A write to TIC-L is effectlvely
a Write to TIL-L). Next, the high-order count value is
written to TIC-H, (the value is simultaneously written into
TIL-Hl, and TIL-L is transferred to TIC-L. Countdown
begins on 42 following the write TIC-H and decrements
at the 92 rate. Tl interrupt occurs when the counters
resch “0”. Generation of a negative pulse on PB7 is done
in the same manner, except ACR bit 7 must be a one. PB7
will go low after a Write TIC-H and go high again when
the counters resch “0”.
The Tl interrupt flag is res.% by either writing TIC-H
fstarting a new count) or by reading TIC-L.
Timing for the one-shot mode is illustrated in Figure 18.
Timer 1 Free-Run Mode
The most important advantage associated with the latches
in Tl is the ability to produce a continuous series of evenly
spaced interrupts and the ability to produce a Square wave
on PB7 whose frequency is not affected by variations in
the processor interrupt response time. This is accomplished
in the “free-running” mode.
In the free-running mode, the interrupt flag is set and the
Signal on PB7 is inverted each time the counter reaches
Zero. However, instead of continuing to decrement from
zero after a time-out, the timer automatically transfers
the contents of the latch into the counter (16 bits) and
continues to decrement from there. lt is not necessary to
rewrite the timer to enable setting the interrupt flag on the
next time-out. The interrupt flag tan be cleared by reading
TIC-L, by writing directly into the flag as will be described
later, or if a new count value is desired by a write to TIC-H.
All interval timers in the UM6522/A are “re-triggerable”.
Aewriting the counter will always re-initialize the time-out
period. In fact, the time-out tan be prevented completely
if the processor continues to rewrite the timer before it
reaches Zero. Timer 1 will operate in this manner if the
processor w r i t e s i n t o t h e h i g h Order counter (TlC-Hl.
However, by loading the latches only, the processor tan
access the timer during each down-counting Operation
without affecting the time-out in process. I nstead, the
data loaded into the latches will determine the length of’
the next time-out period. This capability is particularly
valuable in the free-running mode with the output enabled.
In this mode, the Signal on PB7 is inverted and the interrupt
flag is set with each time-out. By responding to the inter-
r u p t s w i t h new data for the latches, the processor tan ^I
determine the period of the next half cycle during each
half cycle of the output Signal an PB7. In this manner,
very complex waveforms tan be generated. Timing for the
free-running mode is shown in Figure 19.
PB7 OUTPUT
Figure 19. Timer 1 Free-Run Mode Timing
’
Note. A precaution to take when using PB7 as the timer output concerns the data direction Register contents for PB7.
60th DDRB bit 7 and ACR bit 7 must be “1” for PB7 to function as the timer output. If either is a “0”. then PB7 functions
as a normal output pin, controlled by ORB bit 7.
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