TM4C1294NCZAD Datasheet, PDF (948/1914 Pages) Texas Instruments – Tiva Microcontroller

External Peripheral Interface (EPI)
Register 44: EPI Host-Bus 8 Timing Extension (EPIHB8TIME4), offset 0x31C
Important: The MODE field in the EPICFG register determines which configuration is enabled.
For EPIHB8TIME4 to be valid, the MODE field must be 0x2.
EPI Host-Bus 8 Timing Extension (EPIHB8TIME4)
Base 0x400D.0000
Offset 0x31C
Type RW, reset 0x0002.2000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
IRDYDLY
reserved
Type RO
RO
RO
RO
RO
RO
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
CAPWIDTH
reserved
WRWSM
reserved
RDWSM
Type RO
RO
RW
RW
RO
RO
RO
RO
RO
RO
RO
RW
RO
RO
RO
RW
Reset
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:26
25:24
Name
reserved
IRDYDLY
Type
RO
RW
Reset
0x00
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CS3n Input Ready Delay
Value Description
0 reserved
1 Stall begins one EPI clocks past iRDY low being sampled on
the rising edge of EPIO clock.
2 Stall begins two EPI clocks past iRDY low being sampled on
the rising edge of EPIO clock.
3 Stall begins three EPI clocks past iRDY low being sampled on
the rising edge of EPIO clock.
23:14
13:12
reserved
CAPWIDTH
RO
0x002 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Bits [18:16] have the same RTL implementation as the HB16TIMEn
register, even though this is not used in HB8 mode. Thus, the reset
value of 0x2 is carried over from the PSRAMSZ bits of HB16TIMEn.
RW
0x2
CS3n Inter-transfer Capture Width
Controls the delay between Host-Bus transfers.
Value Description
0x0 Reserved
0x1 1 EPI clock.
0x2 2 EPI clock.
0x3 Reserved
948
June 18, 2014
Texas Instruments-Production Data