TM4C1294NCZAD Datasheet, PDF (548/1914 Pages) Texas Instruments – Tiva Microcontroller

Hibernation Module
■ Tamper Register Status
The tamper status is indicated by the STATE bit field of the HIB Tamper Status (HIBTPSTAT)
register. The register bits are reset to 0x0 on cold POR. When the tamper I/O is
enabled/configured, the STATE field shows 0x1. The STATE field is set to 0x2 when a tamper
event is detected. The software may reset the trigger source and the STATE field by writing to
the TPCLR bit in the HIBTPCTL register.
■ System Event Response
When a tamper event is detected, an NMI is generated. The NMI handler is responsible for
performing any other system responses, including a simulate POR. If the tamper event was an
XOSC fail condition, the part switches to the HIB LFIOSC. Once XOSC is stable, the XOSC may
be enabled as the clock source once again.
■ Hibernate Memory Clearing
On a tamper event, software has the option to clear all, the upper half, lower half, or none of the
Hibernate memory. The feature is controlled through the MEMCLR field of the HIBTPCTL register.
■ Wake from Hibernate
A tamper event will assert a wake event to the MCU if the WAKE bit in the HIBTPCTL register is
set.
Tamper Event Logging
Up to four tamper events are stored in HIB Tamper Log n (HIBTPLOGn) registers within the
Hibernate module. When a tamper event occurs the following status is logged:
■ The RTC seconds or calendar values of year, minutes, day of month, hours and seconds in the
HIBTPLOG0/2/4/6 registers
Note: 24-hour mode must be used if RTC calendar mode is enabled. This mode is selected
by setting the CAL24 bit in HIB Calendar Control (HIBCALCTL) register.
■ The tamper status of the TMPRn pins and the XOSCn pins in the HIBTPLOG1/3/5 registers. The
HIBTPLOG7 register captures the OR of all events occurring after the 3rd event is logged in the
HIBTPLOG5 register.
On the assertion of a qualified tamper event (rising edge) on any of the TMPRn pins or an XOSC
failure signal, the current status of all tamper inputs are logged in the HIBTPLOGn register.
Clearing a Tamper Event
After a tamper event, the HIB Tamper Log (HIBTPLOGn) registers and the NMI to the processor
may be cleared by writing a 1 to the TPCLR bit in the HIBTPCTL register. This clear status is reflected
by the STATE bit in the HIBSTPSTAT register changing from 0x2 back to a 0x1. If the source of the
tamper event comes from an XOSC failure, the clearing of a tamper event is delayed while the clock
is switched to LFIOSC. The NMI interrupt handler may access the module immediately, but should
read the HIBTPLOGn registers before issuing a tamper clear in the HIBTPCTL register.
Note: The HIBTPLOG7 register is sticky and is only cleared by a Hibernate module reset.
548
June 18, 2014
Texas Instruments-Production Data