TM4C1294NCZAD Datasheet, PDF (781/1914 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1294NCZAD Microcontroller
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508
The GPIODR8R register is the 8-mA drive control register. Each GPIO signal in the port can be
individually configured without affecting the other pads. When setting the DRV8 bit for a GPIO signal,
the corresponding DRV2 bit in the GPIODR2R register and DRV4 bit in the GPIODR4R register are
automatically cleared by hardware. The 8-mA setting is also used for high-current operation.
Note: There is no configuration difference between 8-mA and high-current operation. The additional
current capacity results from a shift in the V_OH/V_OL levels. See “Recommended Operating
Conditions” on page 1844 for further information.
Note: This register has no effect on port pins PL6 and PL7.
GPIO 8-mA Drive Select (GPIODR8R)
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (AHB) base: 0x4006.0000
GPIO Port K (AHB) base: 0x4006.1000
GPIO Port L (AHB) base: 0x4006.2000
GPIO Port M (AHB) base: 0x4006.3000
GPIO Port N (AHB) base: 0x4006.4000
GPIO Port P (AHB) base: 0x4006.5000
GPIO Port Q (AHB) base: 0x4006.6000
GPIO Port R (AHB) base: 0x4006.7000
GPIO Port S (AHB) base: 0x4006.8000
GPIO Port T (AHB) base: 0x4006.9000
Offset 0x508
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DRV8
Type RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:8
7:0
Name
reserved
DRV8
Type
RO
RW
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00 Output Pad 8-mA Drive Enable
Value Description
0 The drive for the corresponding GPIO pin is controlled by the
GPIODR2R or GPIODR4R register.
1 The corresponding GPIO pin has 8-mA drive.
Setting a bit in either the GPIODR2 register or the GPIODR4 register
clears the corresponding 8-mA enable bit. The change is effective on
the next clock cycle.
June 18, 2014
781
Texas Instruments-Production Data