TM4C1294NCZAD Datasheet, PDF (879/1914 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1294NCZAD Microcontroller
Bit/Field
23
22
21
20
19
18
Name
XFFEN
XFEEN
WRHIGH
RDHIGH
ALEHIGH
WRCRE
Type
RW
RW
RW
RW
RW
RW
Reset
0
Description
External FIFO FULL Enable
Value Description
0 No effect.
1 An external FIFO full signal can be used to control write cycles.
If this bit is set and the FFULL signal is high, XFIFO writes are
stalled.
0
External FIFO EMPTY Enable
Value Description
0 No effect.
1 An external FIFO empty signal can be used to control read
cycles. If this bit is set and the FEMPTY signal is high, XFIFO
reads are stalled.
0
WRITE Strobe Polarity
Value Description
0 The WRITE strobe for CS0n is WRn (active Low).
1 The WRITE strobe for CS0n is WR (active High).
0
READ Strobe Polarity
Value Description
0 The READ strobe for CS0n is RDn (active Low).
1 The READ strobe for CS0n is RD (active High).
1
ALE Strobe Polarity
Value Description
0 The address latch strobe for CS0n is ALEn (active Low).
1 The address latch strobe for CS0n is ALE (active High).
0
PSRAM Configuration Register Write
Used for PSRAM configuration registers.
With WRCRE set, the next transaction by the EPI will be a write of the CR
bit field in the EPIHBPSRAM register to the configuration register (CR)
of the PSRAM. The WRCRE bit will self clear once the write-enabled CRE
access is complete.
Value Description
0 No Action.
1 Start CRE write transaction for CS0n.
June 18, 2014
879
Texas Instruments-Production Data