TM4C1294NCZAD Datasheet, PDF (591/1914 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1294NCZAD Microcontroller
Register 21: HIB Tamper Control (HIBTPCTL), offset 0x400
The Tamper Control (HIBTPCTL) register provides control of the module.
Note:
Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the WRC bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 539. The HIBIO register and bits RSTWK, PADIOWK and
WC of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL
register has been set may produce unexpected results.
Note: Errant writes to the Tamper registers are protected by the Hibernate HIBLOCK register.
HIB Tamper Control (HIBTPCTL)
Base 0x400F.C000
Offset 0x400
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
15
Type RO
Reset
0
14
13
reserved
RO
RO
0
0
12
11
10
9
8
WAKE reserved
MEMCLR
RO
RW
RO
RW
RW
0
0
0
0
0
7
6
5
reserved
RO
RO
RO
0
0
0
20
RO
0
4
TPCLR
W1C
0
19
18
17
RO
RO
RO
0
0
0
3
2
1
reserved
RO
RO
RO
0
0
0
16
RO
0
0
TPEN
RW
0
Bit/Field
31:12
11
Name
reserved
WAKE
Type
RO
RW
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Wake from Hibernate on a Tamper Event
Value Description
0 Do not wake from hibernate on a tamper event.
1 Wake from hibernate on a tamper event.
10
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9:8
MEMCLR
RW
0
HIB Memory Clear on Tamper Event
Value Description
0x0 Do not Clear HIB memory on tamper event.
0x1 Clear Lower 32 Bytes of HIB memory on tamper event
0x2 Clear upper 32 Bytes of HIB memory on tamper event
0x3 Clear all HIB memory on tamper event
June 18, 2014
591
Texas Instruments-Production Data