TM4C1294NCZAD Datasheet, PDF (1325/1914 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1294NCZAD Microcontroller
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Master Interrupt Mask (I2CMIMR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
I2C 6 base: 0x400C.2000
I2C 7 base: 0x400C.3000
I2C 8 base: 0x400B.8000
I2C 9 base: 0x400B.9000
Offset 0x010
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
Type RO
Reset
0
14
13
reserved
RO
RO
0
0
12
11
10
9
8
7
6
5
4
3
2
1
0
RXFFIM TXFEIM RXIM TXIM ARBLOSTIM STOPIM STARTIM NACKIM DMATXIM DMARXIM CLKIM
IM
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:12
11
Name
reserved
RXFFIM
Type
RO
RW
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Receive FIFO Full Interrupt Mask
Value Description
0 The RXFFRIS interrupt is suppressed and not sent to the
interrupt controller.
1 The Receive FIFO Full interrupt is sent to the interrupt controller
when the RXFFRIS bit in the I2CMRIS register is set.
10
TXFEIM
RW
0
Transmit FIFO Empty Interrupt Mask
Note:
The TXFEIM interrupt mask bit in the I2CMIMR register should
be clear (masking the TXFE interrupt) when the master is
performing an RX Burst from the RXFIFO and should be
unmasked before starting a TX FIFO transfers.
Value Description
0 The TXFERIS interrupt is suppressed and not sent to the
interrupt controller.
1 The Transmit FIFO Empty interrupt is sent to the interrupt
controller when the TXFERIS bit in the I2CMRIS register is set.
June 18, 2014
Texas Instruments-Production Data
1325