TM4C1294NCZAD Datasheet, PDF (1253/1914 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1294NCZAD Microcontroller
3. Set the MODE bit to 0x1 and the FSSHLDFM bit to 1 in the SSICR1 register. To operate in the
master mode, program the MS bit to 0. Program the remaining bits in the SSICR0 and SSICR1
register to relevant values.
4. Fill the Tx FIFO with one data byte.
5. Set the EOM bit in the SSICR1 register.
6. Fill the Tx FIFO with one data byte.
17.5
Register Map
Table 17-5 on page 1253 lists the QSSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that QSSI module’s base address:
■ QSSI0: 0x4000.8000
■ QSSI1: 0x4000.9000
■ QSSI2: 0x4000.A000
■ QSSI3: 0x4000.B000
Note that the QSSI module clock must be enabled before the registers can be programmed (see
page 392). The Rn bit of the PRSSI register must be read as 0x1 before any QSSI module registers
are accessed.
Table 17-5. SSI Register Map
Offset Name
Type
0x000 SSICR0
0x004 SSICR1
0x008 SSIDR
0x00C SSISR
0x010 SSICPSR
0x014 SSIIM
0x018 SSIRIS
0x01C SSIMIS
0x020 SSIICR
0x024 SSIDMACTL
0xFC0 SSIPP
0xFC8 SSICC
0xFD0 SSIPeriphID4
0xFD4 SSIPeriphID5
0xFD8 SSIPeriphID6
0xFDC SSIPeriphID7
0xFE0 SSIPeriphID0
RW
RW
RW
RO
RW
RW
RO
RO
W1C
RW
RO
RW
RO
RO
RO
RO
RO
Reset
Description
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0003
0x0000.0000
0x0000.0000
0x0000.0008
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.000D
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0022
QSSI Control 0
QSSI Control 1
QSSI Data
QSSI Status
QSSI Clock Prescale
QSSI Interrupt Mask
QSSI Raw Interrupt Status
QSSI Masked Interrupt Status
QSSI Interrupt Clear
QSSI DMA Control
QSSI Peripheral Properties
QSSI Clock Configuration
QSSI Peripheral Identification 4
QSSI Peripheral Identification 5
QSSI Peripheral Identification 6
QSSI Peripheral Identification 7
QSSI Peripheral Identification 0
See
page
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June 18, 2014
Texas Instruments-Production Data
1253