TM4C1294NCZAD Datasheet, PDF (214/1914 Pages) Texas Instruments – Tiva Microcontroller

JTAG Interface
4.3.4.2
4.3.4.3
alternate hardware function (AFSEL[3:0] set in the Port C GPIO Alternate Function Select
(GPIOAFSEL) register) on the JTAG/SWD pins. See page 777, page 783, page 785, and page 788.
It is possible for software to configure these pins as GPIOs after reset by clearing AFSEL[3:0] in
the Port C GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or
board-level testing, this provides four more GPIOs for use in the design.
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the TM4C1294NCZAD microcontroller. If the program code loaded into flash immediately changes
the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and
halt the controller before the JTAG pin functionality switches. As a result, the debugger may be locked
out of the part. This issue can be avoided with a software routine that restores JTAG functionality
based on an external or software trigger. In the case that the software routine is not implemented and
the device is locked out of the part, this issue can be solved by using the TM4C1294NCZAD Flash
Programmer "Unlock" feature. Please refer to LMFLASHPROGRAMMER on the TI web for more
information.
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is provided for the GPIO pins that can be used as the four
JTAG/SWD pins and the NMI pin (see “Signal Tables” on page 1782 for pin numbers). Writes to
protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 777), GPIO
Pull Up Select (GPIOPUR) register (see page 783), GPIO Pull-Down Select (GPIOPDR) register
(see page 785), and GPIO Digital Enable (GPIODEN) register (see page 788) are not committed to
storage unless the GPIO Lock (GPIOLOCK) register (see page 790) has been unlocked and the
appropriate bits of the GPIO Commit (GPIOCR) register (see page 791) have been set.
Communication with JTAG/SWD
Because the debug clock and the system clock can be running at different frequencies, care must
be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state,
the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software
should check the ACK response to see if the previous operation has completed before initiating a
new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock
(TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have
to be checked.
Recovering a "Locked" Microcontroller
Note:
Performing the sequence below restores the non-volatile registers discussed in “Non-Volatile
Register Programming-- Flash Memory Resident Registers” on page 617 to their factory
default values. The mass erase of the Flash memory caused by the sequence below occurs
prior to the non-volatile registers being restored.
In addition, the EEPROM is erased and its wear-leveling counters are returned to factory
default values when performing the sequence below.
If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate
with the debugger, there is a debug port unlock sequence that can be used to recover the
microcontroller. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while
holding the microcontroller in reset mass erases the Flash memory. The debug port unlock sequence
is:
1. Assert and hold the RST signal.
2. Apply power to the device.
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June 18, 2014
Texas Instruments-Production Data