THS789 Datasheet, PDF (9/34 Pages) Texas Instruments – THS789 Quad-Channel Time Measurement Unit (TMU)

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THS789
SLOS776A – SEPTEMBER 2012 – REVISED DECEMBER 2015
7.3 Feature Description
7.3.1 Counter, Latches, Clock Multiplier
The center of the TMU is a master synchronous counter that counts continuously at a rate of 1.2 GHz. This is the
master timing generator for the whole TMU and defines the basic timing interval of 833 ps, which is further
subdivided with Interpolator circuitry. The output bits of the counter are connected to five sets of latches, which
can latch and hold the counter state on command from each of the channels. In this way, when an event occurs,
the counter time is recorded in the particular channel’s latches. The latch output is converted to CMOS levels
and passed to the respective channel’s FIFO buffer, which is 15 samples deep. The counter 1.2-GHz clock is
derived from the MCLK input to the TMU at 200 MHz. This MCLK input is critical to the accuracy of the TMU, and
any error in frequency is reflected as errors in time measurement. Likewise, jitter propagates to the counter and
other circuits and adds noise to the measurement accuracy. The 200-MHz clock is the input to a clock multiplier.
The clock multiplier uses delay-lock loop (DLL) techniques and combinatorial logic to construct a six-times clock
from the reference input. This 1.2-GHz clock is passed to a high-power clock buffer, which drives all the circuitry
in the master counter and many other circuits in the TMU.
7.3.2 Channels, Interpolator
There are four event channels and one sync channel. The event channels are identical, and the sync channel
contains most of the event channel circuitry, but without a FIFO. An input pulse to the sync channel serves as
the reference time zero for the TMU. An event input to a channel is compared to the sync time reference, and the
time delay is calculated as the time difference modified by a calibration value. An event input follows the
following signal path: the event input edge sets a fast latch (hit latch). The output of the latch is current-buffered
and applied to the interpolator. The interpolator uses DLL techniques to subdivide the counter interval of 833 ps
into 64 time intervals of 13 ps each. A large array of fast latches triggered by the hit latch captures the state of
the 64 time intervals and logically determines 6 bits of timing data based on where the event occurred in the
833-ps clock interval. These 6 bits are latched and eventually passed to the FIFO, where they become the LSBs
of the time-to-data conversion. A synchronizer circuit is also connected to the 64-latch array and removes the
possible timing ambiguity between the 64 latches and the master counter. This takes a few 1.2-GHz clock
pulses. When this process is complete, a pulse occurs which captures the master counter bits into the channel
latches. A subsequent pulse loads all the bits from the interpolator and the counter into the channel FIFO. While
this is happening, the hit latch is being reset, and the channel is prepared to accept another event edge. This
process is fast enough to accept and measure event edges as close together as 5 ns.
7.3.3 FIFO
Each event channel contains a 15-deep, 40-bit-wide FIFO, which allows for rapid accepting and measurement of
event inputs and a user-defined data-output rate of those measurements.
7.3.4 Calibration, ALU, Tag, Shifter
The output of the FIFO is controlled by the shifter, which is a free-running parallel-to-serial register. The shifter
generates a load pulse, which transfers the data in the FIFO output into an arithmetic logic unit, which does the
sync time and calibration time subtractions and then parallel-loads the result into the output serial register. An
LVDS output buffer outputs the clock, data, and strobe signals to transfer the time-measurement data to the user.
A TAG bit is appended to the leading edge of the data word. Currently the TAG feature is not implemented. The
bit will always be 0 representing data.
7.3.5 Serial Interface, Temperature, Overhead
The TMU functions and options are controlled and read out by a serial interface built in CMOS logic that can
operate up to 50 MB/s. There is one central controller which then drives registers, counters, and so on, in each
channel. A temperature sensor is located central to the chip and outputs a voltage proportional to the chip
temperature. If the chip temperature rises above 141°C, the TMU powers down and outputs an overtemperature
alarm signal. The TMU does not restart without a command through the serial interface. A bias circuit provides a
regulated current bias and voltage reference for the TMU. The serial controller sequences some of the bias
circuits to account for some acquisition times, and thereby, turns on the TMU.
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