THS789 Datasheet, PDF (14/34 Pages) Texas Instruments – THS789 Quad-Channel Time Measurement Unit (TMU)

THS789
SLOS776A – SEPTEMBER 2012 – REVISED DECEMBER 2015
Programming (continued)
7.5.1.10 Write Operations to Multiple Destinations
This is similar to the single-write operation except the parallel-load bit is set to 1.
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Hstrobe
HCLK
1
2
3
4
5
6
7
8
9 10 11 12 13 14
24 25 26 27 28 29
1^st clock for next
transaction = 30
Hdata
R₁ /W 1 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12
Register Address (A7:A0)
Data In
D2 D1 D0 w0 X X R/W
Data transfer protocol for parallel write operation
Figure 4. Write Operations to Multiple Destinations
T0426-01
7.5.2 Serial-Results Interface and ALU
7.5.2.1 Event Latches
A selectable rising or falling edge of an event pulse sets the latch. The latch remains set until the interpolator has
finished processing the event, at which time the interpolator resets the latch. The latch, however, does not accept
another event pulse until the event input returns to its initial state and remains for the initial event-pulse duration.
Any event transitions which occur before the interpolator has completed processing the previous event are
ignored. For example, assume that rising edge is selected. Two rising edges can occur as quickly as 5 ns apart.
The falling edge can occur anywhere from 250 ps after the rising edge to 250 ps before the next rising edge. Any
other edges or glitches are ignored.
7.5.2.2 FIFO
Timestamps are written to a FIFO at high speed and read for further processing at a lower speed before being
sent to the result interface. This FIFO is 15 bits deep and 40 bits wide. There are four FIFOs in THS789 device,
one for each channel. There are two status registers (FIFO_Full_x and FIFO_Empty_x), which are set when a
FIFO reaches its full capacity and when it is empty, respectively.
Timestamps are taken and loaded into the FIFO as events occur. Timestamps are mathematically processed by
an arithmetic logic unit (ALU) which calculates the difference between the event and the sync timestamps and
factors in the appropriate calibration value from the calibration register. The ALU operates on the data as it is
read out of the FIFO and sent out through the serial-results interface. The serial-results interface controls the
output of the FIFO.
7.5.2.3 Result-Interface Operation
The TMU initiates a read cycle by setting the strobe signal, Rstrobe, to a low state, indicating that the data
transfer is about to begin. The serial Rdata sequence starts with a TAG bit, followed by the 40-bit data (R0 to
R39). R39 (MSB) is the sign bit. Following the last data bit (R39), the strobe signal (Rstrobe) goes high for two
clock cycles, indicating the end of the transaction.
The data is clocked out of the TMU on the rising edge of RCLK. The receiving device clocks the data in on the
rising edge of RCLK. Figure 5 shows a 40-bit result on the result interface.
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