THS789 Datasheet, PDF (26/34 Pages) Texas Instruments – THS789 Quad-Channel Time Measurement Unit (TMU)

THS789
SLOS776A – SEPTEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
8.2.2.3 Master Clock Input and Clock Multiplier
All of the internal timing of the TMU is derived from the 200-MHz master clock. Therefore, its quality is critical to
the accurate operation of the TMU. Absolute accuracy of the master clock linearly affects the accuracy of the
measurements. This imposes little burden upon the master clock, as accurate oscillators are easy to procure or
distribute. However, the jitter of the master clock is also highly critical to the single-event precision of the TMU
and should be absolutely minimized (< 3-ps RMS). A carefully selected crystal oscillator can meet this
requirement. However, jitter can build up quite quickly in a clock distribution scheme and must be carefully
controlled. Be careful that the LVDS input to the master clock is not badly distorted or that the rise and fall times
are slow (> 0.6 ns).
Discussion of the clock multiplier follows: The TMU operates from a master-clock frequency of 1200 MHz, which
implies a measurement period of 0.833 ns. The master counter runs from this frequency, and all the other clocks
are divided down from this main clock. An interpolator allows finer precision in time measurement, as discussed
elsewhere. The clock multiplier is the circuit that takes the 200-MHz master-clock reference and generates from
that the high quality 1200-MHz clock. The clock multiplier consists of five major sections: First is the delay-lock
loop (DLL), which is a series connection of 12 identical and closely matched variable time-delay circuits. A single
control voltage connects to each of the delay elements. The master 200-MHz clock connects to the input of the
DLL. Because the period of 200 MHz is 5 ns, if the control voltage is adjusted to make the time delay of the DLL
equal to 5 ns, the input and the output of the delay line is exactly phase matched. A phase detector connected to
the input and the output of the delay line can sense this condition accurately, and a feedback loop with a low-
offset-error amplifier is included in the clock multiplier to achieve this result. These are the second and third
circuit blocks. With 12 equally spaced 200-MHz clock phases, select out six equally spaced 833-ps-wide pulses
with AND gates and combine these pulses into a single 1200-MHz clock waveform with a six-input OR gate. The
last circuit element is a powerful differential signal buffer to distribute the 1200-MHz clock to the various circuit
elements in the TMU. The DLL feedback loop is fairly narrowband, so some time is required to allow the DLL to
initialize at start-up (about 100 μs, typical). The DLL is insensitive to the duty cycle of the input 200-MHz clock.
Duty cycles of 40/60 to 60/40 are acceptable. What matters most is as little jitter as possible.
8.2.2.4 Temperature Measurement and Alarm Circuit
Chip temperature of the TMU is monitored by a temperature sensor located near the center of the chip. A small
buffer outputs a voltage proportional to the absolute temperature of the TMU. The buffer drives a load of up to
100 pF typical (50 pF minimum) and open circuit to 10 kΩ to ground resistive. The output voltage slope is 5 mV,
typical. Therefore, the output voltage equation is as follows:
Output Voltage = (Temperature in °C × 5 mV) + 1.365 V
(5)
Also included in the TMU is an overtemperature comparator. At approximately 140°C, the alarm goes active, and
at approximately 7°C below this temperature, the alarm becomes inactive (hysteresis of 7°C prevents tripping on
noise and comparator oscillations). If the alarm goes active, the chip powers down and sets a bit in the serial
register.
An alarm output pin is provided that is an open-drain output. Connect this output through a pullup resistor to the
3.3-V power supply. The resistor must be at least 3.3 kΩ. This creates a slow-speed, low-voltage CMOS digital
output with a logical 1 being the normal operating state and a logical 0 being the overtemperature state.
8.2.2.5 LVDS-Compatible I/Os
The Event, SYNC, and master-clock inputs are LVDS-compatible input receivers optimized for high-speed and
low-time-distortion operation. The Rdata, Rstrobe, and RCLK outputs are similarly LVDS-compatible output
drivers optimized for high-speed/low-distortion operation, driving 50-Ω transmission lines. Typically, LVDS data
transmission is thought of in terms of 100-Ω twisted-wire-pair (TWP) transmission lines. TWP is not applicable to
printed wiring boards and high-speed operation. Therefore, the THS789 device interfaces were designed to
operate most effectively with 50-Ω, single-ended transmission lines. Instead of a current-mode output with its
correspondingly high output impedance, a more-nearly impedance-matched voltage-mode output driver is used.
This minimizes reflections from mismatched transmission line terminations and the resulting waveform distortion.
The input receivers do not include the 100-Ω terminating resistor, which must be connected externally to the
THS789 device. This was done to accommodate daisy-chaining the THS789 inputs. Input offset voltage was
minimized, and the fail-safe feature in the LVDS standard was eliminated in order to minimize distortion.
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