THS789 Datasheet, PDF (15/34 Pages) Texas Instruments – THS789 Quad-Channel Time Measurement Unit (TMU)

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Programming (continued)
THS789
SLOS776A – SEPTEMBER 2012 – REVISED DECEMBER 2015
Rstrobe
RCLK
Rdata
0 0 0 R0 R1 R2 R3 R4 R5
R34 R35 R36 R37 R38 R39 0 0 0 R0 R1 R2 R3 R4 R5 R6 R7
TAG
TAG = 0, Valid Data
Result Data
Sign bit when
programmed
Cycle
End
New Cycle
Figure 5. Result-Interface Operation A
T0428-01
NOTE
In Figure 5, only RCLK_P is drawn to indicate the correct edge with respect to data.
NOTE
The THS788/789 TMU generates a result data ready strobe signal (RSTROBEx).
RSTROBEx asserts when data is driven out from the serial shift register in channel x.
Where x represents channel A,B,C, or D. The RSTROBEx signals intended to drive active
low differential signal indicating start and completion of data on the RDATAx serial output.
There are some circumstances that cause the RSTROBEx signal to deassert one RCLK
cycle early. This behavior remains consistent for each channel after powerup or a reset.
To workaround this potential issue, it is recommended to use leading edge of RSTROBEx
assertion, and capture the correct number of results bits independent of the deassertion of
RSTROBEx.
7.5.2.4 Serial Results Latency
The event stored in the FIFO will be transferred to ALU and subsequently to the free running results data shift
register when the shift register enters a load pulse. The load pulse is generated once per ALU/shift register
processing cycle. The load pulse will trigger the ALU and transfer result to the parallel to serial shift register for
output. The cycle time of the load pulse is dependent upon the depth of the result transfer register and data rate.
Because the results parallel to serial register are free running, the load pulse will be asynchronous to the actual
event. So, the latency will depend upon where in the current cycle the load pulse occurred relative to the event
being captured into the FIFO.
The worst case for data to be output from serial bus:
T_event + 5(R_clkcycles) + (R_datalength + 3) x R_clkcycles + (R_datalength + 3) × R_clkcycles
(1)
The best case for data to be output from serial bus:
T_event + 5(R_clkcycles) + (R_datalength + 3) × R_clkcycles
where
• T_event = 5 ns (minimum repeat capture time)
• 5(R_clkcycles) = number cycles for FIFO to ALU to Shift register
• R_clkcycles is period of R_CLK data = 300 MHz, SDR = 3.33 ns
• R_datalength = number of results bits = 40 for THS789 device
(2)
In the case where R_CLK = 300 MHz, with 40-bit serial result:
Min Latency = 5 ns + 17 ns + (40 + 3) × 3.33 ns = 165 ns
(3)
Max Latency = 5 ns + 17 ns + (40 + 3) × 3.33 ns + (40 + 3) × 3.33 ns = 308 ns
(4)
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