THS789 Datasheet, PDF (27/34 Pages) Texas Instruments – THS789 Quad-Channel Time Measurement Unit (TMU)

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THS789
SLOS776A – SEPTEMBER 2012 – REVISED DECEMBER 2015
8.2.2.6 LVDS-Compatible Inputs
The four event inputs, the sync input and the master-clock input all use the same input interface circuitry.
Figure 10 is a simplified schematic diagram of the LVDS-compatible receiver input stage. The input signal is
impedance-transformed and level-shifted with a PNP emitter-follower and translated into ECL-like differential
signals with a common-emitter amplifier. There is no internal termination resistor and no internal pullup or
pulldown resistors. Unused inputs may be tied off by connecting both input terminals to ground. If the input
terminals are left floating, they are protected by ESD clamps from damage; however, noise may be injected into
the THS789 device and may degrade accuracy. The peak input voltage limits are 0.6 V to 1.7 V. Outside of
these limiting voltages, parts of the input circuit may saturate and distort the timing.
VCC
R
R
2.5 nH
Bond Wire
IN
0.5 pf
Package
0.1 pf
Bond Pad
0.4 pf
VCC
2.5 nH
Bond Wire
IN
0.5 pf
Package
0.1 pf
Bond Pad
0.4 pf
Figure 10. Simplified Schematic of the LVDS Input
S0389-01
Figure 11 shows the typical input connections. The transmission line lengths must be matched from the driver to
the THS789 input [< 0.5 inch (1.27 cm) difference] and terminated in a 100-Ω resistor placed close [< 0.25 inch
(0.635 cm)] to the TMU input pins. The resistor total tolerance should be below 5%. The power dissipation is
below 5 mW, so small surface-mounted resistors are preferred.
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