LMH2190 Datasheet, PDF (9/32 Pages) National Semiconductor (TI) – Quad Channel 27 MHz Clock Tree Driver with I2C Interface

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Connection Diagram
4
CLK2
CLK_
REQ2
CLK_
REQ3
LMH2190
SNAS473H – JUNE 2009 – REVISED MAY 2013
CLK3
3
CLK1
CLK_
REQ1
CLK_
REQ4
CLK4
2
Enable
V_SS
SCLK_
REQ
SCL
1
V_BAT
V_Out
SCLK_IN
SDA
A
B
C
D
Figure 5. 16-Bump DSBGA
See YFQ0016 Package
Pin
C1
C2
A3
B3
A4
B4
D4
C4
D3
C3
A2
D2
D1
A1
B1
B2
Pin Name
SCLK_IN
SCLK_RQ
CLK1
CLK_REQ1
CLK2
CLK_REQ2
CLK3
CLK_REQ3
CLK4
CLK_REQ4
ENABLE
SCL
SDA
V_BAT
V_OUT
V_SS
Port/Direction
Host
Host
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Host
Host
Host/Bidrectional
Battery/Input
LDO/Output
Ground
PIN DESCRIPTIONS⁽¹⁾
Type DESCRIPTION
I
Source Clock Input
O
Source Clock Request
O
Clock Output 1
I
Clock Request Input 1
O
Clock Output 2
I
Clock Request Input2
O
Clock Output 3
I
Clock Request Input 3
O
Clock Output 4
I
Clock Request Input 4
I
Enable Device, Active High
I
I²C Clock Input, 100 kΩ Pull-up to ENABLE
I/O
I²C Data I/O, 100 kΩ Pull-up to ENABLE
Power Power Supply
Power Power Supply to Clock Source and Clock Outputs
Ground Ground Pin
(1) I = Input, O = Output, I/O = Input / Output
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