LMH2190 Datasheet, PDF (4/32 Pages) National Semiconductor (TI) – Quad Channel 27 MHz Clock Tree Driver with I2C Interface

LMH2190
SNAS473H – JUNE 2009 – REVISED MAY 2013
www.ti.com
3.5 V DC AND AC ELECTRICAL CHARACTERISTICS ⁽¹⁾⁽²⁾
Unless otherwise specified, all limits are specified at T_A = 25°C, V_BAT = 3.5V, f_{SCLK_IN} = 26 MHz, C_OUT = 2.2 µF, V_{DD_IO} = 1.8V
(See Figure 6 ) ⁽³⁾, I_OUT = 1 mA, Registers are in default setting. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Condition
Min ⁽⁴⁾
Typ ⁽⁵⁾
Max ⁽⁴⁾
Units
Supply Current ⁽⁶⁾
I_DD
Active Supply Current
Shutdown Supply Current
Clock outputs toggling at 26 MHz
without external capacitors on
CLK1/2/3/4, LDO is ON, I_OUT = 0 mA
In Shutdown. No clocks toggling. LDO
is OFF
In Shutdown. Input CLK toggling, no
Clock outputs toggling. LDO is OFF
3
mA
0.1
1
μA
0.1
1
I_DDQ
Quiescent Supply Current
I_DDEN
Current to Enable pin
No Clock outputs toggling. LDO is ON,
I_OUT = 0 mA
No Clock outputs toggling, LDO is ON,
I_OUT = 10 mA
I²C port is operational
I²C port is idle
36
60
μA
50
80
300
μA
0.1
C_PD
Power Dissipation Capacitance Defined with respect to V_OUT = 1.8V
per CLK output, ⁽⁷⁾
15.7
17.5
pF
Clock Outputs (CLK1/2/3/4)
tp_LH
Propagation Delay SCLK_IN to 50% to 50%
CLK1 - Low to High, Figure 1 ⁽⁷⁾
6.5
10
ns
tp_HL
Propagation Delay SCLK_IN to 50% to 50%
CLK1 - High to Low, Figure 1 ⁽⁷⁾
7.5
11
ns
t_SKEW
Skew Between Outputs (Either
Edge), Figure 1, ⁽⁷⁾
t_RISE
t_FALL
CLK_DC
Rise Time, Figure 3, ⁽⁷⁾⁽⁸⁾
Fall Time, Figure 3 ⁽⁷⁾⁽⁸⁾
Output Clock Duty Cycle,
Figure 3, ⁽⁷⁾
CLK1 to CLK2, 50% to 50%
CLK2 to CLK3 and CLK3 to CLK4,
50% to 50%
C_L = 10 pF to 50 pF, 20% to 80%
C_L = 10 pF to 50 pF, 80% to 20%
C_L = 10 pF to 50 pF
3
6
8.5
ns
1
3.5
7.3
3
6
ns
2.5
5
42
50
58
%
Jitter_RMS Additive RMS period Jitter
BW = 100 Hz to 1 MHz
CLK1
CLK2
CLK3
100
240
fs
330
CLK4
400
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that T_J = T_A. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where T_J > T_A.
(2) C_BAT, C_OUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
(3) V_{DD_IO} is equal to V_OUT when the LDO is enabled and it is equal to V_ENABLE when it is disabled.
(4) Limits are 100% production tested at 25°C. Limits over temperature range are specified through correlations using statistical quality
control (SQC) method.
(5) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
(6) I_DD current depends on switching frequency and load.
(7) This parameter is specified by design and/or characterization and is not tested in production.
(8) Appropriate output load register must be set.
4
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