LMH2190 Datasheet, PDF (5/32 Pages) National Semiconductor (TI) – Quad Channel 27 MHz Clock Tree Driver with I2C Interface

LMH2190
www.ti.com
SNAS473H – JUNE 2009 – REVISED MAY 2013
3.5 V DC AND AC ELECTRICAL CHARACTERISTICS ⁽¹⁾⁽²⁾ (continued)
Unless otherwise specified, all limits are specified at T_A = 25°C, V_BAT = 3.5V, f_{SCLK_IN} = 26 MHz, C_OUT = 2.2 µF, V_{DD_IO} = 1.8V
(See Figure 6 ) ⁽³⁾, I_OUT = 1 mA, Registers are in default setting. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Condition
Min ⁽⁴⁾
Typ ⁽⁵⁾
Max ⁽⁴⁾
Units
Phase
Noise
CLK1 Additive Phase Noise with
all Outputs toggling
f = 100 Hz
f = 1 kHz
-130
-144
f = 10 kHz
-152
f = 100 kHz
-158
f = 1 MHz
-165
CLK2 Additive Phase Noise with
all Outputs toggling
f = 100 Hz
f = 1 kHz
-128
-139
f = 10 kHz
-146
f = 100 kHz
-151
CLK3 Additive Phase Noise with
all Outputs toggling
f = 1 MHz
f = 100 Hz
f = 1 kHz
-153
-127
-138
dBc/Hz
f = 10 kHz
-144
f = 100 kHz
-148
f = 1 MHz
-150
CLK4 Additive Phase Noise with
all Outputs toggling
f = 100 Hz
f = 1 kHz
-125
-135
f = 10 kHz
-142
f = 100 kHz
-147
f = 1 MHz
-148
V_OH
CLK1/2/3/4 Output Voltage High CLK1/2/3/4 = -2 mA
Level
V_OL
CLK1/2/3/4 Output Voltage Low CLK1/2/3/4 = 2 mA
Level
1.6
V
0.2
R_OFF
Output Impedance when disabled LDO enabled
LDO disabled
grounded
diode to ground
System Clock Input (SCLK_IN)
V_IH
SCLK_IN Input Voltage High Level DC Mode
AC Mode
0.65 x
V_OUT
1.2
2.0
V
1.8
V_IL
SCLK_IN Input Voltage Low Level DC Mode
AC Mode
0
0.35 x
V_OUT
V
0
0.6
I_IH
SCLK_IN Input Current High Level SCLK_IN = 1.8V, Clock path disabled
0
0.1
µA
I_IL
SCLK_IN Input Current Low Level SCLK_IN = V_SS, Clock path disabled
-0.1
0
µA
C_IN
Input Capacitance ⁽⁹⁾
7.5
10
pF
V_BIAS
DC Bias Voltage
AC Mode
0.805
V
R_IN
Input Resistance
AC Mode, Clock path enabled.
21
30
kΩ
(9) This parameter is specified by design and/or characterization and is not tested in production.
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