LMH2190 Datasheet, PDF (20/32 Pages) National Semiconductor (TI) – Quad Channel 27 MHz Clock Tree Driver with I2C Interface

LMH2190
SNAS473H – JUNE 2009 – REVISED MAY 2013
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Transferring Data
Every frame on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver
must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been
addressed must generate an acknowledge after each byte has been received.
After the START condition, the I²C master sends a chip address (Figure 29). This address is seven bits long
followed by an eight bit which is a data direction bit (R/W). For the eighth bit, a “0” indicates a WRITE and a “1”
indicates a READ. The second byte selects the register to which the data will be written. The third byte contains
data to write to the selected register.
MSB
LSB
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 R/W
Bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
I²C SLAVE address (chip address)
Figure 29. I²C Chip Address
Register changes take effect at the SCL rising edge during the last ACK from slave. An example of a WRITE
cycle is given in Figure 30. When a READ function is to be accomplished, a WRITE function must precede the
READ function, as shown in the Read Cycle waveform (Figure 31).
ack from slave
ack from slave
ack from slave
start MSB Chip Address LSB w ack MSB Register 0x02h LSB ack MSB Data LSB ack stop
SCL
SDA
start
slave address =
38_h or 0111000₂
w ack register address = 0x02h ack
register 0x02h data
Figure 30. Example I²C Write Cycle
ack stop
ack from slave
ack from slave repeated start
ack from slave data from slave ack from master
start MSB Chip Address LSB w ack MSB Register 0x00h LSB ack rs MSB Chip Address LSB r ack _{MSB Data LSB} ack stop
SCL
SDA
start
slave address =
38_h or 0111000₂
w ack register address = 0x05h ack rs
slave address =
38_h or 0111000₂
Figure 31. Example I²C Read Cycle
r ack register 0x05h data ack stop
I²C Timing
The timing of the SDA and SCL signals is depicted in Figure 32 and the parameters are given in Table 1.
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