LMH2190 Datasheet, PDF (12/32 Pages) National Semiconductor (TI) – Quad Channel 27 MHz Clock Tree Driver with I2C Interface

LMH2190
SNAS473H – JUNE 2009 – REVISED MAY 2013
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, T_A = 25°C, V_BAT = 3.5V, f_{SCLK_IN} = 26 MHz, C_OUT = 2.2 µF, V_{DD_IO} = 1.8V (See Figure 19),
Registers are in default configuration.
Additive Phase Noise
vs.
Frequency Offset
-100
CLK1 Response, C_L = 10 pF
-110
-120
SCLK_IN
-130
-140
-150
-160
CLK1
CLK2
CLK3 _CLK4
CLK1
-170
-180
100
1k
10k
100k
1M
DRIVE STRENGTH = 10 - 15 pF
FREQUENCY OFFSET (Hz)
Figure 13.
TIME (5 ns/DIV)
Figure 14.
CLK1 Response, C_L = 22pF
CLK1 Response, C_L = 33 pF
SCLK_IN
SCLK_IN
CLK1
DRIVE STRENGTH = 15 - 22.5 pF
TIME (5 ns/DIV)
Figure 15.
CLK1 Response, C_L = 50 pF
SCLK_IN
CLK1
DRIVE STRENGTH = 33.5 - 50 pF
TIME (5 ns/DIV)
Figure 17.
CLK1
DRIVE STRENGTH = 22.5 - 33.5 pF
TIME (5 ns/DIV)
Figure 16.
Power Supply Rejection Ratio
vs.
Frequency
100
80
60
40
20 _{IOUT = 10 mA}
V_BAT: No capacitors
0 ^{VOUT: 2.2 #F and 100 nF}
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 18.
12
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