LMH2190 Datasheet, PDF (16/32 Pages) National Semiconductor (TI) – Quad Channel 27 MHz Clock Tree Driver with I2C Interface

LMH2190
SNAS473H – JUNE 2009 – REVISED MAY 2013
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SCLK_IN
CLK1
CLK2
CLK3
CLK4
SCLK_IN
CLK1
CLK2
CLK3
CLK4
Figure 21. Clock Outputs Timing: With Skew only Figure 22. Clock Outputs Timing: With Skew and
Inversion
CLOCK REQUEST LOGIC
The clock request logic enables an independent control of the clock tree driver outputs (CLK1 to CLK4) as well
as an overall source clock request (SCLK_REQ) and LDO enabling. Since the clock request logic always needs
to be active, it is supplied by either the output of the LDO (V_OUT) or by the external ENABLE. Further details
about the selection between V_OUT and ENABLE can be found in the LOW DROPOUT REGULATOR section later
in the datasheet.
Clock Request Inputs
A clock request input is provided for each clock output (Figure 23). This allows the peripheral device to control
the LMH2190 when it wants to receive a clock. In case the peripheral device does not have clock request
functionality, the CLKx_REQ can be wired to a logic high level to enable the clock output (in default register
setting). Alternatively, it can be controlled through I²C. The CLKx_REQ input can be configured to be active high
or active low. When the LDO is off, the clock request logic still need to be powered such that it can turn on the
LDO. This is why the ENABLE input is used to power the Clock Request Logic in case the LDO is off. Although
the CLK_REQ logic is supplied with 1.8V LDO voltage (or ENABLE), the CLKx_REQ input can tolerate voltages
up to V_BAT.
To prevent glitches on CLK outputs, enabling of the outputs is done synchronously. A latch is used to ensure that
the CLK outputs will be enabled on the falling edge of the source clock input (SCLK_IN).
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