LMH2190 Datasheet, PDF (15/32 Pages) National Semiconductor (TI) – Quad Channel 27 MHz Clock Tree Driver with I2C Interface

LMH2190
www.ti.com
SNAS473H – JUNE 2009 – REVISED MAY 2013
Clock Tree Driver Input
The source clock input (SCLK_IN) is the input for the clock tree driver. It can be configured to DC or AC coupled
mode. In shutdown mode, the input stage is completely switched off to prevent unnecessary power consumption
when the source clock is still present.
In the DC coupled mode, the clock input may range from 32 kHz to 27 MHz. DC coupling mode requires that the
input is a square wave.
In AC mode an external capacitor needs to be connected in series with the clock source and the SCLK_IN pin to
block external DC. Internally, a DC bias network centers it at about V_OUT/2. This enables the use of a sine wave
clock source with a amplitude between 0.8 V_PP and 1.8 V_PP. The bias voltage is enabled only when the clock
request output is activated in order to eliminate the DC power. In the AC coupled mode, the clock input may
range from 13 MHz up to 27 MHz. It is assumed to be a sine wave. Signals with sharp edges, such as square
wave signals, should be prevented as the DC control loop will not be able to maintain its internal DC level.
Clock Tree Driver Outputs
The LMH2190's clock tree driver outputs have many modes of operation to reduce power consumption and
minimize EMI. The output drive strength of the LMH2190 can be selected in 4 steps based on the load
capacitance it needs to drive. The configuration can be done via the I²C interface.
There are two dedicated methods for reducing EMI that can be selected through the I²C interface. As shown in
Figure 21 and Figure 22 the first method (default) skews all of the clock edges individually, so that the EMI
generated by the switching is spread out over time. The second method inverts two of the outputs and also
skews one pair from the other.
CLK1 ENABLE
CLK INPUT TYPE
REG00-Bit4
SCLK_IN
DC
1
AC ₀
SKEW
SETTING
CLK2 ENABLE
CLK3 ENABLE
CLK TREE
REG00-Bit0
CLK4 ENABLE
Figure 20. Clock Tree Driver
CLK1
CLK1 LOAD
REG01-Bit0:1
CLK2
CLK2 LOAD
REG02-Bit0:1
CLK3
CLK3 LOAD
REG03-Bit0:1
CLK4
CLK4 LOAD
REG04-Bit0:1
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