LMH2190 Datasheet, PDF (21/32 Pages) National Semiconductor (TI) – Quad Channel 27 MHz Clock Tree Driver with I2C Interface

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LMH2190
SNAS473H – JUNE 2009 – REVISED MAY 2013
SDA
8
7
2
SCL
1
6
8
1
5
3
4
Figure 32. I²C Timing Diagram
10
7
9
Symbol
f_SCL
1
2
3
4
5
5
6
7
8
9
10
C_b
Table 1. I²C Timing
Parameter
Clock Frequency
Hold Time (repeated) START Condition
Clock Low Time
Clock High Time
Setup Time for a Repeated START Condition
Data Hold Time (Output direction, delay generated by
LMH2190)
Data Hold Time (Input direction, delay generated by the
Master)
Data Setup Time
Rise Time of SDA and SCL
Fall Time of SDA and SCL
Set-up Time for STOP condition
Bus Free Time between a STOP and a START Condition
Capacitive Load for Each Bus Line
Limit
Min
Max
400
0.6
1.3
600
600
300
900
0
900
100
20+0.1 C_b
300
10+0.1 C_b
300
600
1.3
10
200
Units
kHz
µs
ns
ns
ns
µs
ns
ns
ns
ns
ns
µs
pF
I²C Registers
Table 2. Configuration Register⁽¹⁾
Field
Output Mode
Clock Request Output Type
Clock Request Output Polarity
Clock Request Output Mode
Bits
Description
[0]
Sets the timing relationship of the clock
outputs (Figure 21 and Figure 22).
0 - All 4 outputs are skewed from each
other
1 - Two pair of outputs where one output of
the pair is the inversion of the other and the
second pair is skewed from the first pair.
[1]
Sets whether the output is push-pull or open
drain.
0 - Push-Pull Output
1 - Open Drain/Source Output (Open drain
with Active low output, Open source with
Active high output).
[2]
Sets whether the clock request output is
active low or active high.
0 - Active low output
1 - Active high output
[3]
Sets how the clock request output operates.
0 - Use clock request inputs
1 - Force the clock request output to be
asserted.
(1) Address = 00H, type = R/W, reset value = 44H, 0100_0100, Bold face settings are the default configuration.
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