LMH2190 Datasheet, PDF (22/32 Pages) National Semiconductor (TI) – Quad Channel 27 MHz Clock Tree Driver with I2C Interface

LMH2190
SNAS473H – JUNE 2009 – REVISED MAY 2013
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Table 2. Configuration Register⁽¹⁾ (continued)
Field
Clock Input Type
LDO Mode
Reserved
Bits
[4]
[6-5]
[7]
Description
Sets whether the input is AC or DC coupled.
0 - AC coupled
1 - DC coupled
Sets the regulator mode of operation.
00 - OFF
01 - Reserved
10 - Track Clock Requests
11 - Force ON
Table 3. CLK1 Output Register⁽¹⁾
Field
CLK1 Load
CLK_REQ1 Input Polarity
CLK_REQ1 Force ON Control
CLK_REQ1 Force OFF Control
CLK_REQ1 Pull down Resistor
Reserved
Reserved
Bits
[1-0]
[2]
[3]
[4]
[5]
[6]
[7]
Description
Sets the drive strength of the clock output
based on the capacitive load.
00 - 10pF to 15pF
01 - 15pF to 22.5pF
10 - 22.5pF to 33.5pF
11 - 33.5pF to 50pF
Sets whether a logic low or high enables the
clock output.
0 - Logic low enables the clock output.
1 - Logic high enables the clock output.
Selects whether to use a clock request or
I²C logic to enable the output.
0 - Use the clock request pin to control
the output.
1 - Force the clock output to be enabled
(Force ON).
Selects whether to use a clock request or
I²C logic to disable the output.
0 - Use the clock request pin to control
the output.
1 - Force the clock output to be disabled
(Force OFF). ”Force OFF" overrides ”Force
ON".
Selects whether an internal 200 kΩ pull
down resistor on the clock request input to
GND is present.
0 - No internal pull down resistor is
present.
1 - Internal 200 kΩ pull-down resistor is
present.
(1) Address = 01H, type = R/W, reset value = 06H, 0000_0110, Bold face settings are the default configuration.
Field
CLK2 Load
CLK_REQ2 Input Polarity
Table 4. CLK2 Output Register⁽¹⁾
Bits
[1-0]
[2]
Description
Sets the drive strength of the clock output
based on the capacitive load.
00 - 10pF to 15pF
01 - 15pF to 22.5pF
10 - 22.5pF to 33.5pF
11 - 33.5pF to 50pF
Sets whether a logic low or high enables the
clock output.
0 - Logic low enables the clock output.
1 - Logic high enables the clock output.
(1) Address = 02H, type = R/W, reset value = 06H, 0000_0110, Bold face settings are the default configuration.
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