LMH0340SQE Datasheet, PDF (9/30 Pages) Texas Instruments – 3 Gbps, HD, SD, DVB-ASI SDI Serializer and Cable Driver With LVDS Interface

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FUNCTIONAL DESCRIPTION
LMH0040, LMH0050
LMH0070, LMH0340
SNLS271I – APRIL 2007 – REVISED APRIL 2013
DEVICE OPERATION
The SER is used in digital video signal origination equipment. It is intended to be operated in conjunction with an
FPGA host which preprocesses data for it, and then provides this data over the five bit wide data path. Provided
the host has properly formatted the data for the SER, the output of the device will be compliant with DVB-ASI,
SMPTE 259M-C, SMPTE 292M or SMPTE 424M depending upon the output mode selected.
Texas Instruments offers IP in source code format to perform the appropriate formatting of the data, as well as
evaluation platforms to assist in the development of target applications. For more information please contact your
local Texas Instruments Sales Office/Distributor.
POWER SUPPLIES
The SER has several power supply pins, at 2.5V as well as 3.3V. It is important that these pins all be connected,
and properly bypassed. Bypassing should consist of parallel 4.7μF and 0.1μF capacitors as a minimum, with a
0.1μF capacitor on each power pin. The device has a large contact in the center of the bottom of the package.
This contact must be connected to the system GND as it is the major ground connection for the device. A 22 μF
capacitor is required on the V_DDPLL pin which is connected to the 3.3V rail.
Discrete bypassing is ineffective above 30 MHz to 50 MHz in power plane-based distribution systems. Above this
frequency range, the intrinsic capacitance of the power-ground system can be used to provide additional RF
bypassing. To make the best use of this, make certain that there are PCB layers dedicated to the Power supplies
and to GND, and that they are placed next to each other to provide a distributed capacitance between power and
GND.
The SER will work best when powered from linear regulators. The output of linear regulators is generally cleaner
with less noise than switching regulators. Output filtering and power system frequency compensation are
generally simpler and more effective with linear regulators. Low dropout linear regulators are available which can
usually operate from lower input voltages such as logic power supplies, thereby reducing regulator power
dissipation. Cascading of low dropout regulators should not be done since this places the entire supply current
load of both load systems on the first regulator in the cascade and increases its loading and thermal output.
POWER UP
The 3.3V power supply should be brought up before the 2.5V supply. The timing of the supply sequencing is not
important. The device has a power on reset sequence which takes place once both power supplies are brought
up. This sequence will reset all register contents to their default values, and will place the PLLs into link
acquisition mode, attempting to lock on the TXCLK input.
RESET
There are three ways in which the device may be reset. There is an automatic reset which happens on power-up;
there is a reset pin, which when brought low will reset the device, with normal operation resuming when the pin is
driven high again. The third way to reset the device is a soft reset, implemented via a write to the reset register.
This reset will put all of the register values back to their default values, except it will not affect the address
register value if the SMBus default address has been changed.
LVDS INPUTS
The SER has LVDS inputs that conform with the ANSI/TIA/EIA-644–A Standard. These inputs have an internal
100 Ω resistor across the inputs which allows for the closing of a current loop interface from the LVDS driver in
the host. It is recommended that the PCB trace between the FPGA and the transmitter be less than 25cm.
Longer PCB traces may introduce signal degradation as well as channel skew which could cause serialization
errors. This connection between the host and the SER should be over a controlled impedance transmission line
with an impedance which matches the termination resistor – usually 100 Ω. Setup and hold times are specified in
LVDS Switching Characteristics, however there is the ability to change these by use of the CLK delay adjustment
available via the SMBus, and writing to register 0x30'h.
Copyright © 2007–2013, Texas Instruments Incorporated
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Product Folder Links: LMH0040 LMH0050 LMH0070 LMH0340