LMH0340SQE Datasheet, PDF (12/30 Pages) Texas Instruments – 3 Gbps, HD, SD, DVB-ASI SDI Serializer and Cable Driver With LVDS Interface

LMH0040, LMH0050
LMH0070, LMH0340
SNLS271I – APRIL 2007 – REVISED APRIL 2013
www.ti.com
CML Output Interfacing
The LMH0050 does not include the internal SMPTE cable driver, as its outputs are CML, include internal 50 Ω
pull up resistors, and are intended to drive 100 Ω transmission lines. The LMH0050 outputs may either be
connected to a differential transmission medium such as twisted pair cable, or used to drive an external cable
driver.
Power Down Mode
If the device is not to be used, some power can be saved by writing a ‘0x40h’ to register 0x26'h, and a 0x10'h to
register 0x01'h. The write to register 0x26'h will disable the input buffers of the device, and the write to register
0x01'h will power down the output buffer. In this mode, the device power dissipation can be expected to be
reduced by approximately 30%. There are portions of the circuit which will automatically power down if there is
no clock present on the TXCLK input, so this method can be used to further reduce the power.
SMBus INTERFACE
The configuration bus conforms to the System Management Bus (SMBus) 2.0 specification. SMBus 2.0 includes
multiple options. The optional ARP (Address Resolution Protocol) feature is not supported. The I/O rail is 3.3V
only and is not 5V tolerant. The use of the SMB_CS signal is recommended for applications with multi-drop
applications (multiple devices to a host).
The SMBus is a two wire interface designed for the communication between various system component chips,
additional signals maybe required for chip select function depending upon application. By accessing the control
functions of the circuit via the SMBus, signal count is kept to a minimum while allowing a maximum amount of
versatility. The SMBus has three pins to control it: an SMBus CS pin which enables the SMBus interface for the
device, a Clock and a Data line. In applications where there might be several SER devices, the SDA and SCK
pins can be bussed together and the individual devices to be communicated with may be selected via their
respective SMB_CS pin. The SCK and SDA are both open drain and are pulled high by external pullup resistors.
The SER has several internal configuration registers which may be accessed via the SMBus. These registers are
listed in Table 2.
TRANSFER OF DATA TO THE DEVICE VIA THE SMBus
During normal operation the data on SDA must be stable during the time when SCK is high.
START / STOP / IDLE CONDITIONS
There are three unique states for the SMBus:
START
STOP
IDLE
A HIGH-to-LOW transition on SDA while SCK is High indicates a message START condition
A LOW-to-HIGH transition on SDA while SCK is High indicates a message STOP condition.
If SCK and SDA are both High for a time exceeding t_BUF from the last detected STOP condition or if they are high for
a total exceeding the maximum specification for t_HIGH then the bus will transfer to the IDLE state.
SMBus TRANSACTIONS
A transaction begins with the host placing the SER SMBus into the START condition. Then a byte (8 bits) is
transferred, MSB first, followed by a ninth ACK bit. ACK bits are ‘0’ to signify an ACK, or ‘1’ to signify NACK.
After this the host holds the SCK line Low, and waits for the receiver to raise the SDA line as an ACKnowledge
that the byte has been received.
REGISTER WRITE
To write a data value to a register in the SER, the host writes three bytes to the SER. The first byte is the device
address—the device address is a 7 bit value, and if writing to the SER the last bit (LSB) is set to ‘0’ to signify that
the operation is a write. The second byte written is the register address, and the third byte written is the data to
be written into the addressed register. If additional data writes are performed, the register address is
automatically incremented. At the end of the write cycle the host places the bus in the STOP state.
REGISTER READ
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