LMH0340SQE Datasheet, PDF (23/30 Pages) Texas Instruments – 3 Gbps, HD, SD, DVB-ASI SDI Serializer and Cable Driver With LVDS Interface

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ADD
'h
29
Name
LOS Status
2A
Event Status
2B-2D
2E
Reserved
Reverse Bit Order
2F
Reserved
30
CLK_Delay
LMH0040, LMH0050
LMH0070, LMH0340
SNLS271I – APRIL 2007 – REVISED APRIL 2013
Table 2. SER Register Detail Table (continued)
Bits
Field
R/W
Default
Description
Reading the LOS status register will provide a byte which has six bits which represent the presence or
absence of a signal at each of the LVDS inputs to the SER.
7:6
Reserved
5
LOS_CLK
r
0'b
1: No clock present on TXCLK
0: Clock present
4:0
LOS_Data
r
0'b
1:No data present
0: Data Present(one bit per TX channel)
The event status register has two user readable bits which indicate if the device is locked, and if there is
a signal present on the TXCLK input.
7:4
Reserved
3
TXCLK_detect
r
0'b
1: TXCLK detected
0: TXCLK not detected
2
PLL_lock
r
0'b
1: PLL locked
0: PLL not locked
1:0
Reserved
This bit can be used to reverse the serialization order, however it will only work properly when the device
is NOT in DVB_ASI mode
7
Reserved
6
Reverse Bit Order
r/w
0'b
1: reverses serialization order
0: normal order
5:0
Reserved
The three msbs from this register are used to insert a programmable delay into the TXCLK path, if the
host FPGA does not provide adequate setup and hold times for the SER, this register can be used to
shift the window in 125ps increments.
7:5
TCLK Delay
r/w
011'b
000'b is minimum delay setting, 111'b is
maximum delay setting, each step is
approx 125ps
4:0
Reserved
Copyright © 2007–2013, Texas Instruments Incorporated
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Product Folder Links: LMH0040 LMH0050 LMH0070 LMH0340