LMH0340SQE Datasheet, PDF (22/30 Pages) Texas Instruments – 3 Gbps, HD, SD, DVB-ASI SDI Serializer and Cable Driver With LVDS Interface

LMH0040, LMH0050
LMH0070, LMH0340
SNLS271I – APRIL 2007 – REVISED APRIL 2013
www.ti.com
ADD
'h
1D
1E-20
21
22
23
24
25
26
27
28
Table 2. SER Register Detail Table (continued)
Name
Bits
Field
R/W
Default
Description
Device Type
Reading from this register will return an 8 bit value which indicates which product from the SER family is
being addressed
7:0
Device
r
xx1xxx00 for the LMH0340
xx1xxx01 for the LMH0040
xx1xxx10 for the LMH0070
xx0xxx01 for the LMH0050
Reserved
Mode
This register returns the mode that the device is operating in.
7:2
Reserved
1:0
r/w
11 = DVB ASI mode
01,10, 00 = SDI mode
DVB_ASI Override
In normal operation, the DVB_ASI mode is selected via the external pin. By setting the 0 bit in this
register, the function of this pin is overridden, and the mode is set via register 21'h instead. After setting
this bit, a channel reset must be executed via reg 0x26h, bit 7
7:1
Reserved
0
r/w
0'b
1: contents of register 21h will override
the DVB_ASI pin
0: Pin control
Reserved
LVDS Clock Delay
Bypass
This register selects of the TXCLK delay adjust is enabled or bypassed.
7
r/w
0'b
1: Bypasses TXCLK delay
0: Delay Enabled
6:0
Reserved
Reserved
Powerdown
Individual bits from this register can power down different parts of the SER – to place the part into a low
power standby mode, write a ‘0’ to this register.
7
channel reset
r/w
0'b
Used to reset the channel, needed when
changing between DVB_ASI mode and
normal operating mode via SMBus
6:0
Powerdown
r/w
0x3Fh
for normal operation, write x011 1111b to
this register. For low power mode write
x100 0000b to the register.
Event Disable
The SER keeps counts of various types of events. These include FIFO over/underflows, and loss of the
input signals or clocks. This register allows the user to mask these errors from being counted.
7:5
Reserved
4
PLL_CLK_disable
r/w
0'b
1: Clock Error disabled
0: Clock Errors counted
3
fifo_error_disable
r/w
0'b
1: FIFO Errors ignored
0: FIFO Errors counted
2
TXCLK_detect_disable r/w
0'b
1: TXCLK Detect Errors ignored
0: TXCLK Detect Errors counted
1
CLK_LOS_disable
r/w
0'b
1: CLK_LOS Errors ignored
0: CLK_LOS Errors counted
0
Data_LOS_disable
r/w
0'b
1: Data_LOS Errors ignored
0: Data_LOS Errors counted
LVDS LOS Override These bits are used to force the LOS indicator regardless of the input signal level on the LVDS pins.
Operation
7:2
Reserved
1
LVDS Preset LOS
r/w
0'b
LVDS Preset LOS
1: Forces LOS to be Low
0: normal mode
0
LVDS Reset LOS
r/w
0'b
LVDS Reset LOS
(has priority over Preset)
1: Forces LOS to be High
0: normal mode
22
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