LMH0340SQE Datasheet, PDF (16/30 Pages) Texas Instruments – 3 Gbps, HD, SD, DVB-ASI SDI Serializer and Cable Driver With LVDS Interface

LMH0040, LMH0050
LMH0070, LMH0340
SNLS271I – APRIL 2007 – REVISED APRIL 2013
APPLICATION INFORMATION
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PCB RECOMMENDATIONS
The SMPTE Serial specifications have very stringent requirements for output return loss on drivers. The output
return loss will be degraded by non-idealities in the connection between the SER (all variants with the exception
of the LMH0050) and the output connector. All efforts should be taken to minimize the trace lengths for this area,
and to assure that the characteristic impedance of this trace is 75Ω.
It is recommended that the PCB traces between the host FPGA and the SER be no longer than 10 inches
(25cm) and that the traces be routed as differential pairs, with very tight matching of line lengths and coupling
within a pair, as well as equal length traces for each of the six pairs. For additional information on layout and
soldering of the WQFN package, please refer to the applications note AN-1187 (SNOA401).
PCB Design do’s and don’ts:
• DO Whenever possible dedicate an entire layer to each power supply – this will reduce the inductance in the
supply plane.
• DO use surface mount components whenever possible
• DO place bypass capacitors close to each power pin
• DON’T create ground loops – pay attention to the cutouts that are made in your power and ground planes to
make sure that there are not opportunities for loops.
• DON’T allow discontinuities in the ground planes – return currents will follow the path of least resistance – for
high frequency signals this will be the path of least inductance.
• DO place the SER outputs as close as possible to the edge of the PCB where it will connect to the outside
world.
• DO make sure to match the trace lengths of all differential traces, both between the sides of an individual
pair, and from pair to pair.
• DO remember that VIAs have significant inductance – when using a via to connect to a power supply or
ground layer, two in parallel are better than one.
• DO connect the slug on the bottom of the package to a solid Ground connection. This contact is used for the
major GND connection to the device as well as serving as a thermal via to keep the die at a low operating
temperature.
• There is an application note available which discusses layout suggestions for the SER in greater detail.
TYPICAL SMPTE APPLICATIONS CIRCUIT
A typical application circuit for the LMH0340 is shown in Figure 14. Alternately this could also employ the
LMH0040 or LMH0070 Serializers in lower data rate SMPTE applications.
The TX interface between the host FPGA and the SER is composed of a 5-bit LVDS Data bus and its LVDS
clock. This is a point-to-point interface and the SER includes on-chip 100 terminations. Pairs should be of equal
length to minimize any skew impact. The LVDS clock (TXCLK) uses both edges to transfer the data.
An SMBus is also connected from the host FPGA to the SER. If the SMBus is shared, a chip select signal is
used to select the device being addressed. The SCK and SDA signals require a pull up resistor. The SMB_CS is
driven by a GPO signal from the FPGA. Depending on the FPGA I/O it may also require a pull up unless it is a
push / pull output.
Depending upon the application, several other GPIO signals maybe used. This includes the DVB_ASI and
RESET input signals. If these pins are not used, then must be tied off to the desired state. The LOCK signal
maybe used to monitor the SER. If it is unused, leave the pin as a NC (or route to a test point).
The SER includes a SMPTE compliant cable driver. While this is a differential driver, it is commonly used single-
endedly to drive 75 Ω coax cables. External 75 Ω pull up resistors are used to the 2.5V rail. The active output(s)
also includes a matching network to meet the required Output Return Loss SMPTE specification. While
application specific, in general a series 75 Ω resistor shunted by a 6.8 nH inductor will provide a starting value to
design with. The signal is then AC coupled to the cable with a 4.7 µF capacitor. If the complementary output is
not used, simply terminate it after its AC coupling capacitor to ground. This output (even though its inverting) may
still be used for a loop back or 1:2 function due to the nature of the NRZI coding that the SMPTE standards
require. The output voltage amplitude of the cable driver is set by the R_SET resistor. For single-ended
applications, an 8.06 kΩ resistor is connected between this pin and ground to set the swing to 800mV.
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