LMH0340SQE Datasheet, PDF (17/30 Pages) Texas Instruments – 3 Gbps, HD, SD, DVB-ASI SDI Serializer and Cable Driver With LVDS Interface

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LMH0040, LMH0050
LMH0070, LMH0340
SNLS271I – APRIL 2007 – REVISED APRIL 2013
The PLL loop filter is external for the SER. A capacitor is connected in series to a resistor between the LF_CP
and LF_REF pins. Typical values are 500 Ω and 0.1 µF.
There are several configuration pins that requiring setting to the proper level. The RSVD_H pins should be pulled
High to the 3.3V rail with a 5 kΩ resistor. Depending upon the application the DVB_ASI pin may be tied off or
driven.
There are three supply connections (see PLL FILTER / BYPASS and for recommendations). The two main
supplies are the 3.3V rail and the 2.5V rail. There is also a 3.3V connection for the PLL circuitry.
There are multiple Ground connections for the device. The main ground connection for the SER is through the
large center DAP pad. This must be connected to ground for proper device operation. In addition, multiple other
inputs are required to be connected to ground as show in Figure 14 and listed in .
All Bypass
CAPS not
shown
3.3V 2.5V
3.3V
1,36
47 ₊
48 ^{T- X4}
45
46
+-TX3
43 ₊
44 ^-TX2
41 ₊
42 ^-TX1
39 ₊
40 ^-TX0
37 ₊
38 ^{T- XCLK}
3.3V
3.3V
5 k:
7,15,18,
25,35 2,5
DAP,8,9,10,12,13,
21,22,23,24,29
2.5V
75Ö
16
TXOUT+
17
TXOUT-
75Ö ^{6.8 nH}
SDI Output
4.7 PF
4.7 PF
75Ö
75Ö
3.3V
V_DDPLL ²⁸
14 ^{8.06 kÖ}
RSET
22 PF
LMH0340
26
LF_REF
0.1 PF
1 kÖ
1 kÖ
32
SDA
33
SCK
34
SMB_CS
27
LF_CP
3
GPIO_0
GPIO_1 ⁴
GPIO_2 ¹¹
500Ö
6
DVB_ASI
31 _LOCK
30 _RESET
19, 20
DNC
Figure 14. Typical SMPTE Application Circuit
TYPICAL LMH0050 CML APPLICATIONS CIRCUIT
A typical application circuit for the LMH0050 is shown in Figure 15.
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