DS64BR111_13 Datasheet, PDF (9/39 Pages) Texas Instruments – DS64BR111 Ultra Low Power 6.4 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

DS64BR111
www.ti.com
SNLS343C – SEPTEMBER 2011 – REVISED APRIL 2013
ELECTRICAL CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
THD:STA
Hold time after (Repeated) Start
At I_PULLUP, Max
Condition. After this period, the first
0.6
µs
clock is generated.
TSU:STA
Repeated Start Condition Setup
Time
0.6
µs
TSU:STO
Stop Condition Setup Time
0.6
µs
THD:DAT
Data Hold Time
0
ns
TSU:DAT
Data Setup Time
100
ns
T_LOW
T_HIGH
t_F
t_R
t_POR
Clock Low Period
Clock High Period
Clock/Data Fall Time
Clock/Data Rise Time
Time in which a device must be
operational after power-on reset
See ⁽⁶⁾
See ⁽⁶⁾
See ⁽⁶⁾
See⁽⁶⁾ and ⁽⁴⁾
1.3
µs
0.6
50
µs
300
ns
300
ns
500
ms
(6) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
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