DS64BR111_13 Datasheet, PDF (3/39 Pages) Texas Instruments – DS64BR111 Ultra Low Power 6.4 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

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Pin Diagram
DS64BR111
SNLS343C – SEPTEMBER 2011 – REVISED APRIL 2013
OUTA+ 7
OUTA- 8
AD1/EQA1 9
AD0/EQA0 10
INB+ 11
INB- 12
SMBUS AND
CONTROL
24 INA+
23 INA-
22 _VDD
21 _VDD
20 OUTB+
19 OUTB-
(1) The center DAP on the package bottom is the device GND connection. This pad must be connected to GND through
multiple (minimum of 4) vias to ensure optimal electrical and thermal performance.
DS64BR111 Pin Diagram 24 lead
Pin Name
Pin
Number
Differential High Speed I/O's
INA+, INA- ,
INB+, INB-,
24, 23
11, 12
OUTA+, OUTA-,
OUTB+, OUTB-,
Control Pins
ENSMB
7, 8
20, 19
3
ENSMB = 1 (SMBUS MODE)
SCL
5
SDA
4
PIN DESCRIPTIONS
I/O, Type⁽¹⁾
Pin Description
I, CML
O,CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip
50Ω termination resistor connects INx+ to VDD and INx- to VDD when
enabled.
Inverting and non-inverting 50Ω driver outputs with de-emphasis. Compatible
with AC coupled CML inputs.
I, LVCMOS Float
System Management Bus (SMBus) enable pin
Tie HIGH = Register Access, SMBus Slave mode
FLOAT = SMBus Master read from External EEPROM
Tie LOW = External Pin Control Mode
I, LVCMOS
O, Open Drain
I, LVCMOS,
O, OPEN Drain
ENSMB Master or Slave mode
SMBUS clock input pin is enabled. A clock input in Slave mode. Can also be a
clock output in Master mode.
ENSMB Master or Slave mode
The SMBus bidirectional SDA pin is enabled. Data input or open drain (pull-
down only) output.
(1) LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not specified. Unless the
"Float" level is desired; 4-Level input pins require a minimum 1K resistor to GND, VDD (in 2.5V mode), or VIN (in 3.3V mode). For
additional information, Table 1 Table 5
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%
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