DS64BR111_13 Datasheet, PDF (17/39 Pages) Texas Instruments – DS64BR111 Ultra Low Power 6.4 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

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DS64BR111
SNLS343C – SEPTEMBER 2011 – REVISED APRIL 2013
1 :1000000000002000000407002FED4002FED4002FC4
2 :10001000AD4002FAD400005F568005F5A8005F5AE9
3 :100020008005F5A800005454F100000000000000A8
4 :1000300000000000000000000000000000000000C0
5 :1000400000000000000000000000000000000000B0
6 :1000500000000000000000000000000000000000A0
7 :100060000000000000000000000000000000000090
8 :100070000000000000000000000000000000000080
9 :100080000000000000000000000000000000000070
10 : 1 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0
11 : 1 0 0 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0
12 : 1 0 0 0 B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0
13 : 1 0 0 0 C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0
14 : 1 0 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0
15 : 1 0 0 0 E 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
16 : 1 0 0 0 F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17 : 0 0 0 0 0 0 0 1 F F
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CRC-8 based on 40 bytes of
data in this shaded area
Insert the CRC value here
CRC Polynomial = 0x07
MAX EEPROM Burst = 32
Figure 6. Typical EEPROM Data Set
The CRC-8 calculation is performed on the first 3 bytes of header information plus the 37 bytes of data for the
DS64BR111 or 40 bytes in total. The result of this calculation is placed immediately after the DS64BR111 data in
the EEPROM which ends with "5454". The CRC-8 in the DS64BR111 uses a polynomial = x⁸ + x² + x + 1
In SMBus master mode the DS64BR111 reads its initial configuration from an external EEPROM upon power-up.
Some of the pins of the DS64BR111 perform the same functions in SMBus master and SMBus slave mode.
Once the DS64BR111 has finished reading its initial configuration from the external EEPROM in SMBus master
mode it reverts to SMBus slave mode and can be further configured by an external controller over the SMBus.
The connection to an external SMBus master is optional and can be omitted for applications were additional
security is desirable. There are two pins that provide unique functions in SMBus master mode.
• DONE#
• READEN#
When the DS64BR111 is powered up in SMBus master mode, it reads its configuration from the external
EEPROM when the READEN# pin goes low. When the DS64BR111 is finished reading its configuration from the
external EEPROM, it drives the DONE# pin low. In applications where there is more than one DS64BR111 on
the same SMBus, bus contention can result if more than one DS64BR111 tries to take control of the SMBus at
the same time. The READEN# and DONE# pins prevent this bus contention. The system should be designed so
that the READEN# pin from one DS64BR111 in the system is driven low on power-up. This DS64BR111 will take
command of the SMBus on power-up and will read its initial configuration from the external EEPROM. When it is
finished reading its configuration, it will drive the DONE# pin low. This pin should be connected to the READEN#
pin of another DS64BR111. When this DS64BR111 senses its READEN# pin driven low, it will take command of
the SMBus and read its initial configuration from the external EEPROM, after which it will set its DONE# pin low.
By connecting the DONE# pin of each DS64BR111 to the READEN# pin of the next DS64BR111, each
DS64BR111 can read its initial configuration from the EEPROM without causing bus contention.
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